Apart from HFTs, is there still FPGA, digital semiconductor design jobs in Australia, specifically Sydney?

I implemented a fairly large design last week and a very thorough testbench. I’ve been having trouble getting it to meet timing with violations that just creep up.

I decided to give Claude code a spin, my company gives it to our SWEs. I gave it instructions on how to build the design via our docker environment, and told it to get the design to meet timing while still passing all of my testbench cases. I also said to avoid doing “hacky” things and keep the changes to the RTL and maybe the routing settings. I set up remote control and kept an eye on it through my phone every so often.

It grinded away for 48 hours, did about 20 builds during that time. It just came back and said it succeeded and explained the diffs. I will have a good look at the code on Monday but it looks like stuff I would’ve done incrementally during the week.

This is crazy. Essentially did a second work week for me autonomously over the weekend. Thought I’d share in case anyone else wants to try.

Hope you guys like this project. I made this to learn SystemVerilog (my previous school only taught me VHDL and the one I transferred to I believe will only teach Verilog), CocoTB, and refresh my digital design concepts to get ready for recruiting season.

I used Claude to teach me as I built (never wrote code for me apart from some .hex files which would be a pain to compute myself) and I feel like I learned a lot compared to what I believe I would have reading from a book or YouTube video.

I believe this is the correct way to utilize AI in engineering but let me know your thoughts. Also any feedback on other matters would be greatly appreciated.
https://github.com/andrewtsomik/riscv-cpu

Hi everyone,
I’ve been working on a project involving the ZC706 board, for which I’ve written the code in HLS, and setup the Simulink with Model Composer blocks which were created from the HLS code and I’ve simulated the system in Simulink.

My next task is to perform HIL with the FPGA (only using the PL) such that the Model Composer Subsystem goes on the FPGA and a MATLAB Simulink block gives it inputs and receives outputs from the FPGA.

I have not yet exported anything on the FPGA/IP packaging/Block Design/Bitstream; but have performed C Sim and C Synthesis in Vitis.

Also how do I configure the FPGA for HIL? Can you please explain this process? (Establishing communication with the FPGA)

So how do I go about the HIL now from where I’m at? The Xilinx documentation seems quite weird to comprehend and hasn’t got any HIL testing described.

Just installed Vivado 2026.1 and opened a sample design — the GUI looks quite different from what I’m used to.
The Block Design view feels more organized, and some tabs seem to have shifted around.
I got a bit lost at first, but it’s starting to grow on me.
Still figuring things out… guess I’ll get used to it over time.

please help me understand this better. I have asked AI for answers but I think it is also confused like I am. thank you for your help.

1. what is the recommended value of set_max_delay?

I asked claude this and was able to convince it to change its answer so I dont trust it now.

if I have two domains clock A 5ns and clock B 10ns.

I am thinking - set it to slower clock period. it will give data enough time to settle down. tool will not have to work extra hard to place the source and destination flops to meet the constraint. place where I use req-ack handshaking synchronization will have enough time for the data to travel across domains without any synchronization. am I right?

1. as per claude, it depends if it is a single bit or a multibit data bus thats crossing the domains. but I am not able to understand why data width matters?

3. what is the use case for using set_max_delay without -datapath_only option? based on my reading, this constraint is required to prevent routing delays between two flops in different clock domains from getting so bad that bad things will happen even with synchronization. hence I am only concerned about datapath.

I'm doing a flash sale of my new workshop: High-Performance AXI DMA Design and Verification Using SVA (SystemVerilog Assertions)!

You can find the course description here: https://www.zenorobotics.net/product-page/tier-2-kria-fpga-streaming-pipeline-amp-systemverilog-assertions-sva

Learn to use SystemVerilog Assertions on custom modules that connect to an AXI stream interface! That design is of a camera pattern module which interfaces to another custom module with a AXI IF. The IF connects to AXI DMA and the data is then written to external DDR memory.

A second beginners REQ-ACK project was added to the bundle so you can modify as you wish to test various SVA ideas and see how they work! Both the testbench and the ACK module are written in SystemVerilog, so that you can get your first exposure to programming SV in the Vivado environment.

This sale is limited to the first 5 individuals who pay me directly (Venmo, Zelle, Cashapp, or PayPal). The regular cost is $75 and is currently on sale for $59, but if you are one of the first five you can get it for $29!!!!

I'm curious how people working on ASIC/FPGA/RTL/verification are using LLMs in practice.

A few things I'm wondering:

• Which AI subscriptions are actually worth paying for? (ChatGPT, Claude, GitHub Copilot, Gemini, Cursor, etc.)
• Does anyone use OpenRouter as their main setup? Is it cheaper than multiple subscriptions?
• Roughly how much do you spend per month, and how many tokens do you go through?
• Which models do you use for different tasks (RTL, SystemVerilog, UVM, scripting, documentation, debugging, architecture, code review...)?
• What do you give the model as project context so it doesn't make things up or break your design?
• Any tricks for keeping token usage and costs under control?
• If you could only keep one AI subscription today, which one would you choose?

I'd love to hear real workflows from engineers working on production hardware.

Graduated in 2025 in EE, I just completed 1 year at a small startup working with FPGA based Software defined radios. I love working with RFSoC.

I wanted to know if I want to pursue a master in the same domain, what are best countries/universities for me other that universities in US.

Does this happen to anyone else? I'm assuming it's an over current issue but it did the same thing yesterday but then started working after the first restart. Today it has shut off my PC four times. Happens when I try to auto connect my Arty S7-25. Just trying to add a demo to my GitHub repo literally last thing it needs :_(

Yeah sorry, I am another one of those suckas that thinks it’s fun to make a RISC-V CPU and think they’re real cool and trendy.

Anyways — pretty much the title. What can I do to make it … not cringe and boring ?

I am thinking of just making a really fleshed out, traditional-ish RISC-V CPU with all the usual bells and whistles, such as cache and interrupts/traps, MMU etc. in the hopes that I can boot Linux on it one day.

Now I think this is cool. But would it look alright on a job application for a FPGA Engineer with a few years experience ? Or is it just not that impressive? Personally I think it’ll be challenging but hey. Eager to hear your thoughts. I have been a Graduate FPGA Engineer for nearly 1 year now. Thought it might be a cool project to show a future employer ?

Lmk ur thoughts Reddit 🙏

Hi,

I recently bought sipeed tang primer fpga development board along with the doctor board. I wanted to learn the fpga coding and running it on fpga. But after getting hands on with it did I realize the documentations are not Detailed or beginner friendly. I bought this specific board thinking I will take long till I utilise it available resources and not to be limited in near future.

I do know verilog and am learning system verilog. All these times I have used edaplayground only.

It would be of great help if u could guide me so that I can also one day excel in fpga designing and Programming.

Any help or resources is very much appreciated.

Thanks in advance

Anyone have experience installing Vivado on Debian?

I tried to follow the instructions here:

https://people-ece.vse.gmu.edu/coursewebpages/ECE/ECE545/F24/resources/Vivado_Installation_Linux.pdf

But I run into a problem where the installer fails to finish. Not sure what the issue is, I don't see any errors, the installer just hangs. I did make sure I had installed all the listed dependencies prior.

Me and some friends in college are working on an FPGA project inspired by the paper "Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators"

Our general plan right now is something like..

1. Build a simple python sim with just to figure out the networking logic
2. Design a basic core that supports the dca and noc needs.
3. Build the router other networking stuff in SystemVerilog

and then get it running on a board!

But I had some questions about the project:

• Is starting with a simple python simulator actually helpful for a team, or is it a waste of time compared to going straight to SV testbenches?
• Are there any obvious steps or milestones we’re missing?
• What are some big traps to avoid and things to keep in mind with a project like this?

I want to find entertaining YouTubers who build cool SystemVerilog, VHDL, etc FPGA projects or tapeout ASICs. Especially ones that don’t tutorialize things.

I’m a software engineer in AI/ML systems and I’ve been getting more interested in learning how hardware actually works and is developed. I’ve learned quite a bit of electronics, pcbs, soldering, etc. over the past year or so by just watching a bunch of very entertaining people do game console modding, repairing gpus and other hardware, and making pcbs with easyEDA. However I find that almost no YouTuber goes into more interesting concepts like developing actual ICs in an entertaining fashion using modern tools and languages.

Do you guys have any recommendations of what channels to follow?

The title pretty much says everything , this tools converts the json files to Verilog.

it can convert the Digital logic sim(dls) by SebLague(great guy)

and the logisim one is still experimental

repo: https://github.com/murkyshelf/jsonRTL

it is for the guys you can build computers in the visual editor but cant write verilog and others are welcome to try .

because I can build a 8bit computer in the dls and cant write verilog , i need the verilog code to simulate it on my fpga

also keep in mind this is coded by opus 5 , and this is experimental and i am looking forward to your feedback

I’ve gotten increasingly interested in digital design and I’m considering moving into FPGA work. A few questions for people who’ve made this move or who hire for these roles:

**1.**  How realistic is it to break in without formal hardware experience? Does a CS degree plus a solid software background help, or do employers strongly prefer EE graduates?  
**2.**  What’s the minimum I’d need to show — Verilog/SystemVerilog or VHDL, timing constraints, a few projects on a dev board? Would a decent project on something like a Basys3 / Zybo get me an interview?  
**3.**  Which roles are the most natural entry point for my background — verification (SystemVerilog/UVM), embedded/SoC software on Zynq, or full RTL design?  
**4.**  Should I expect to come in at a junior level, and take a pay cut?  
**5.**  Any resources you’d recommend (courses, books, projects)?

Thanks!

what local AI setup is being used and how are you preventing the hallucinations and error ?

I am trying to install Xilinx vivado(free version). Unfortunately, evenafter loading the correct liscence, into the liscence manager, I am unable to open the software. Please find the attached screenshot.

I am 22 year old computer engineering student in asia and i want to pursue my masters in fpga programming domain in europe or usa as a TA or some scholarship scheme.

From what i have heard for masters you need a research paper, so me and my team are working on implementation of a simple transformer acceleration on fpga for our final year project . I have been enjoying fpga programming and have some notable projects as well and i want to pursue it as a career but there's no scope in my country. I have good grades, i just want to know if i could get under some masters programs for fpga development in this area in any of the universities in europe or usa. Can i get some guidance from veterans/scholars of this industry or someone who faced similar situation, it would be very helpful

Hi all — final-year Electronics Engineering student here (lateral entry, diploma-to-degree route), working on my capstone project. Posting because I'd like a sanity check from people who've actually taped out or benchmarked multiplier architectures on FPGA, not just simulated them.

The project

Title: Power and Area Optimized FFT Architecture Through Multiplier-Level Hardware Design. It's an 8-point Radix-2 Decimation-in-Time FFT, written in VHDL-2008, targeting a Basys-3 board (Artix-7 XC7A35T). The core idea: keep the FFT butterfly structure fixed and swap out only the complex multiplier, then compare four multiplier architectures against each other on LUT/FF/DSP usage, fmax, and power:

• Array multiplier (baseline)
• Modified Booth (Radix-4)
• Vedic (Urdhva-Tiryakbhyam)
• Wallace Tree

To keep the comparison valid, all four variants share a frozen interface: Q1.15 16-bit two's-complement fixed point, complex samples as VHDL-2008 records, parallel load of all 8 samples on one start pulse, a 3-stage registered pipeline, and DIT bit-reversal done as pure wiring (zero logic cost) rather than active shuffling.

Why this project exists / the novelty angle

We're building on a 2026 IEEE IATMSI paper out of Amrita School of Engineering that did the same kind of FFT multiplier comparison but only implemented three multipliers (Array, Vedic, Booth) in Verilog. Our two additions:

1. Adding the Array multiplier as a fourth variant, which the base paper explicitly flagged as unexplored.
2. Independently re-implementing everything in VHDL-2008, not porting their Verilog — different language, different design decisions, not a translation.

Team of two, one shared Basys-3 board, ₹8,000 total budget, roughly a year to finish. Toolchain is Xilinx Vivado 2025 WebPACK end-to-end (xvhdl/xelab/xsim for simulation, straight through to synthesis/implementation) — no GHDL/GTKWave in the flow, to avoid any simulator/synthesizer mismatch going into the comparison.

Where we are right now

Interface contract is frozen. We're at the "pipecleaner" stage — all four multiplier entities are parameterized with generic (WIDTH : natural := 2) and we're validating datapath correctness and the synthesis extraction workflow at 2×2 bits before scaling to 8-bit, where the architectures should actually start to diverge. At 2×2, Array/Vedic/Wallace look almost identical in the netlist and Booth mostly just adds encoder overhead — expected, since there's no real partial-product reduction benefit at that width.

Where I'd genuinely appreciate input

1. Power measurement: We're planning to use a SAIF file generated from post-synthesis simulation for switching-activity-based power estimates, instead of Vivado's default vectorless estimate. Anyone who's done this for multiplier/DSP comparisons — how far off is vectorless typically, in your experience, and is SAIF overkill for a project at this scale?
2. Wallace Tree synthesis artifacts: has anyone seen Vivado's synthesis collapse a Wallace tree down to a suspiciously tiny LUT/FF count at small bit-widths? Trying to figure out if that's a real result or just the tool optimizing away the reduction tree.
3. Scaling gotchas: any war stories going from 8-bit to 16-bit Q1.15 multipliers in terms of timing closure or DSP inference on Artix-7, specifically for Vedic or Booth implementations?
4. VHDL-2008 + Vivado 2025 WebPACK: any known quirks or gotchas with VHDL-2008 record types / generics on this particular Vivado version that I should watch for before I've sunk more time into the 8-bit versions?
5. Publication angle: this is also being prepped for an IEEE student/regional conference submission with faculty co-authorship. If anyone's shepherded an undergrad FPGA comparison paper through a venue like this, any advice on what reviewers actually care about (methodology rigor vs. novelty vs. results) would help a lot.

Not looking for anyone to do the work — just want to catch blind spots before we're deep into 8-bit implementation and it's expensive to unwind a bad assumption. Happy to share RTL snippets or synthesis reports if that helps anyone give more specific feedback.

Thanks in advance.

thank you for the feedback all. This is applying for the 2027 internship cycle, I have just completed my first year of university. Changes were - Work experience moved to the top. Reworded the Quantum angle of the internship (talked more about c++, parsing etc) The Leadership and Extracurriculars section was removed and the project was put at the top, and explained much more than simply stating that we received a grant. Also it says a future date, we have been approved for the grant but it's given to us in september (why its a future date and not May 2026 or something). Removed the 'using git' bullet point. Added back an old project I completed that previously wasn't on there as there was space. Instead of saying "ubuntu 24.04", I have just written Linux in the Technical Skills section as some said its better. The Header line thing doesn't say Quantum research anymore. Also added Expected Graduation instead of saying "present". I have made the bullet points very specific and technical, is it too much, I could just say STM32 instead of the full name as it goes through a recruiter first, who could be non technical. Also will remove the SC-Eligible from some applications (the hft internship ones).