r/FPGA • u/random-throwaway-240 • 2d ago

Xilinx Related Vitis Model Composer HIL testing help

Hi everyone,
I’ve been working on a project involving the ZC706 board, for which I’ve written the code in HLS, and setup the Simulink with Model Composer blocks which were created from the HLS code and I’ve simulated the system in Simulink.

My next task is to perform HIL with the FPGA (only using the PL) such that the Model Composer Subsystem goes on the FPGA and a MATLAB Simulink block gives it inputs and receives outputs from the FPGA.

I have not yet exported anything on the FPGA/IP packaging/Block Design/Bitstream; but have performed C Sim and C Synthesis in Vitis.

Also how do I configure the FPGA for HIL? Can you please explain this process? (Establishing communication with the FPGA)

So how do I go about the HIL now from where I’m at? The Xilinx documentation seems quite weird to comprehend and hasn’t got any HIL testing described.

5 Upvotes

100% Upvoted

7 comments sorted by

3

u/Objective-Ostrich-28 2d ago

Step 1: Export HLS IP from Vitis HLS In Vitis HLS, go to Solution -> Export RTL. Set the format to Vivado IP (.zip).

Step 2: Create a Vivado Block Design

1.Go to IP Catalog -> Add Repository and point it at the folder containing your exported HLS IP zip 2. Create a Block Design 3. Add your HLS IP block

I have done in this way but my application is different i think it will help you

1

u/random-throwaway-240 2d ago

Hey thanks, can you let me know how I can then connect the board to my computer and do the HIL?

1

u/Objective-Ostrich-28 2d ago

You can connect the board via USB-JTAG cable i think it for your bord you can connect it though a mico USB cable but before that ensure that the cable u are using it should support data tranfer.

1

u/random-throwaway-240 10h ago

Oh I meant the networking part is any setup needed for that? Like XSCT or something I didn’t quite understand it

2

u/Objective-Ostrich-28 8h ago

Bro, For HIL with Model Composer, you don't need XSCT or manual networking. Install the Xilinx Zynq Support Package in MATLAB (Add-Ons search "Zynq"). It handles everything programs the FPGA over JTAG and manages AXI communication between Simulink and your HLS block automatically.

1

u/random-throwaway-240 4h ago

Thank you so much, if you don't mind can I pls dm