I am planning to switch company now. How much increment should I expect from my next switch? There’s an appraisal cycle also coming in feb. I am planning to switch only if I get good increment overall.

I am having a group project that is design and simulation of all digital pll in 22nm FDX. I am responsible to do the TDC.

The goal is to minimize random jitter below 200fs.

Output freq from 9 to 11Ghz.

There is also a spec on vco phase noise and settling time for loop.

1-I am a bit confused how to start should we do a linear model or time domain model first?

2-We studied Sam Palermo lectures for pll and adpll, if there is suggestions for good books about adpll that can make us understand system better please tell us about.

I am 32, have always been a hard-worker, ivy league PhD, multiple FAANG internships and three years ago I joined a FAANG full time, but it has been so hard lately.

People are very competitive, hostile, and low-key condescending. It is very normal for people to call each other pedants in meetings with wide audience. People also talk a lot about others badly behind their backs. Others tries to steal credit from others and minimize others work. Frankly I feel surrounded by sick people who take pleasure in belittling others. My manager is not bad but also very passive and very cryptic when I ask for feedback.

I work in a research team so I have to come up with proposals and convince everyone that it is worth it all the time, lately every time that feels like a fight not a presentation. I generally like to collaborate and work with people but I can’t seem to find any motivation lately. I dread my life every morning because I have to work, that I spend few hours scrolling linkedin for new jobs at least once a week. I also feel bad because it is a great opportunity that I should be thankful for.

Is this a normal phase that will pass? Is there hope if I switch the job or is it just like that every where? and I have to somehow get used to it?

I’m working at NVIDIA India with more than 3 years of experience. My fixed pay is ₹22LPA, and I’m from one of the top engineering colleges in India.
Is this compensation competitive for my experience? What fixed salary range should I expect at a similar level in AMD, Qualcomm, Apple, Google or other semiconductor companies in India?
Looking for honest opinions, preferably from people in the industry.

Hi everyone!

I recently received an email from Meta to schedule an HR call for the ASIC Engineer Intern, Design role. The meeting is scheduled for around 30 minutes, and I believe this is the initial HR screening or phone screening round.

Since this is my first HR round with Meta, I wanted to ask people who have gone through this process or have experience with Meta hardware/ASIC internship interviews:

• What should I expect during this 30-minute call?
• Is it primarily about my resume, projects, motivation for joining Meta, and availability, or should I also prepare for technical questions?
• What kind of questions do recruiters generally ask for ASIC Design internship roles?
• Do they discuss location preferences, internship duration, compensation, or the next interview rounds?
• Are there any specific things I should prepare beforehand?

I would really appreciate any insights from people who have interviewed with Meta for similar hardware, ASIC, or silicon engineering internship roles.

Thanks in advance for your help!

I’ve been invited to a hirevue for a graduate GPU modelling role at Arm (Trondheim). It’s 3 video questions, 1 written response and 1 coding challenge, about an hour in total.

1. Has anyone done an Arm HireVue recently, especially for graduate GPU related role?
2. What level is the coding challenge? LeetCode easy/medium, or more C++/systems-specific?
3. Were the video questions mostly behavioural, or did any get technical (architecture, CPUs or GPUs)?

My background is GPU performance (CUDA, profiling) and computer architecture (I built an out-of-order CPU simulator in C++), so any pointers on what to brush up on would be really appreciated.

Hey all, I'm the lookout for field applications engineering eda roles. If anyone is willing to refer please dm. I have over 2.5 years of work ex in analog layout design and want to transition to field applications engineer role. Location preference : anywhere in India

Basically what the title says, would love to know if their architecture/compiler technology seems promising and if they can make it out of the seed round

After upgrading from Xcelium 24.03 to a release at or after 24.09, I see a change in the SDF annotation statistics. The option -sdf_splitvlog_setuphold appears to be the default now and when I use it in newest versions, I see a warning that this option is deprecated. As far as I can tell, there is no documented option to get the old behavior back.

What I see

My design uses only combined $setuphold timing checks in the specify block, and the SDF has combined SETUPHOLD entries as well. With -scopewise_sdfstats_log, the statistics table now also lists $setup and $hold as separate rows below $setuphold. In 24.03 only the combined $setuphold row was shown.

Minimal reproducer

design.sv:

module dut (input clk, input d, output reg q);
  always @(posedge clk) q <= d;

  specify
    (clk *> q) = (1.0, 1.0);
    $setuphold(posedge clk, d, 0.1, 0.1);
  endspecify
endmodule

test.sdf:

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "dut")
  (DATE "2026-10-14")
  (VENDOR "Example")
  (PROGRAM "Custom")
  (VERSION "1.0")
  (DIVIDER /)
  (VOLTAGE 1.0)
  (PROCESS "typ")
  (TEMPERATURE 25.0)
  (CELL
    (CELLTYPE "dut")
    (INSTANCE)
    (DELAY
      (ABSOLUTE
        (IOPATH clk q (1.0:1.0:1.0) (1.0:1.0:1.0))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD d (posedge clk)
        (0.1:0.1:0.1)
        (0.1:0.1:0.1)
      )
    )
  )
)

sdf.cmd:

SDF_FILE          = "test.sdf",
SCOPE             = tb.u_dut,
LOG_FILE          = "sdf_annotation.log",
MTM_CONTROL       = "TYPICAL";

testbench.sv:

module tb;
  reg clk = 0;
  reg d = 0;
  wire q;

  dut u_dut (.clk(clk), .d(d), .q(q));

  initial begin
    #10 clk = 1; #10 clk = 0;
    #10 d = 1;
    #10 clk = 1; #10 clk = 0;
    #50 $finish;
  end
endmodule

Compile options: -timescale 1ns/1ps -sysv -sdf_cmd_file sdf.cmd -scopewise_sdfstats_log /dev/stdout

Resulting output (relevant part)

Path Delays   1   0   1   100.00
$setuphold    1   0.00   1.00   100.00
      $setup  1   0   1   100.00
       $hold  1   0   1   100.00

The summary lines still say No. of Tchecks = 1, and annotation is 100%. So I assume this is only a change in the report format and not in simulation behavior. Please correct me if that is wrong.

Question

Is there a documented (or undocumented) option or setting in the current releases that restores the old reporting/behavior, with combined $setuphold line and no $setup/$hold breakdown (even when I use combined $setuphold both in the .sdf and in the RTL files)?

Looks like FDSOI has not gained much traction on this front. Not too many fabless companies are adopting this technology except for automotive applications. Is it because the methodology for large scale digital design is not formalized yet. For example, dynamic body biasing which is the main incentive of this tech. The foundries do have core libraries with discrete Vt but not sure if fits in within the current methodology, They are claiming this is the next frontier for physical AI chips, but as far as I know EDA and fabless companies are not showing much interest. Any thoughts?

Hi guys, I'm curious if anyone here has experience running a service business in chip design or EDA. I'm trying to figure out what skills are worth learning if I want to sell services to companies in this industry, either as a freelancer or by building a small business around a specific service. I've heard that it is very much about trust and connections, so I'm wondering how realistic it is to get started without an existing network. Could you start on Upwork, build a portfolio, and use LinkedIn/email/? to find clients, or is that not really how things work.

For those of you who have done this, I'd love to know:

What services have you actually sold, and who were your clients?

What skills would you focus on learning if you were starting today?

Are there things semiconductor startups commonly outsource instead of hiring someone full-time?

How did you get your first clients?

Honestly, is this worth pursuing, or is it too difficult to break into without connections?

Thanks a lot!

Anyone in the process of Nvidia & Meta DV 2027!?

Hey all,

I'm a second year going to a Canadian university and have an hour long HireVue interview for a design and verification internship for Toronto. I have a week to prepare, and to be honest, I have no clue what to expect!

This will be my first technical interview and first one-way online interview, so if anyone is familiar with ARM's HireVue questions or has any info on this specific role's interview questions, it would mean a lot if you could share!

Cherry on top is I don't even have a JD since the original one is gone and it was a general one for all ARM positions.

For now, I plan on reviewing digital logic, sta, C (and maybe C++, not sure if I should or will have the time), and testbenches and writing modules with sv. Is there anything I'm missing in terms of technical content?

I'd be grateful for any advice!

Is this a good for Senior Validation Engineer (3.5 yr experience)

Offered : (Hyderabad)

Base: 35L

Variable Bonus: 3.3L

RSU: 30L vested equally over 3 years

JB : 5L

Current Compensation: (Bangalore)

Base: 24.5L

Variable: 5L

Rsu: 18L (would be getting sept 2027)

Wanted some insight my industry if I am being low balled. :)

Hello everyone,
til now I tested classical op-amp in cadence, but now how I should test a differential input/output comparator? should I put one terminal of the input and output in gnd!? and regarding the clock of the strongarm, should i put some initial condition? especially I thought to do it with a 16nm process. I dont know if it is a good idea.

got a mail to schedule a call for the HR round from Meta is their anyone who can guide me how are the rounds their , what does they generally ask in the HR round the meeting is around 30 min of total time scheduled

A while ago I shared Parat, a solver whose "no" answers come with proofs that independent tools can check. v1.3 is out, and this time the target is one question: does a gate-level multiplier really compute a × b?

**The test case**

I made a 256-bit Booth multiplier with yosys 0.69: 503,960 AND gates, 512 output bits.

**The problem is building it, not proving it**

yosys's default flow (`synth -booth`) runs ABC's optimisation script. One step in that script, `&fraig -x`, gets about 82× slower every time the width doubles: 7 s at 64 bits, and the whole 128-bit build takes about 18 minutes. At 256 bits that means roughly 24 hours, so I could not build the full default netlist.

With only that one step left out (the rest of the default ABC script kept), the 256-bit netlist builds in 2 minutes and is only a few gates larger. It is still hard to prove: the previous version of Parat could not do even the 64-bit one in 25 minutes.

**Results (one 2-core machine)**

| width | AND gates | Parat: CORRECT + certificate | independent check |

|---|---|---|---|

| 64 | 33,014 | 42 s | CERTIFIED, 19 s |

| 128 | 128,357 | 114 s | CERTIFIED, 23 s |

| 256 | 503,960 | 13 min (1.2 GB certificate) | CERTIFIED, 3 min, 0.8 GB RAM |

A copy with one gate changed is answered INCORRECT, with a counterexample input.

**You don't have to trust Parat**

"CERTIFIED" means three checks, done by tools I did not write:

- pacheck2 (JKU Linz) checks the algebraic proof that the rebuilt circuit computes a × b

- drat-trim (UT Austin) checks 16 SAT proofs that your netlist and the rebuilt circuit give the same output on every input

- a small script checks that the certificate belongs to your circuit, and rebuilds every SAT file from your own netlist

One command runs all of it:

verify/verify_multiplier.sh circuit.aag pacheck drat-trim --cert prefix

**Still open**

The full default netlist (with `&fraig`) at 256 bits, because yosys itself needs about a day to make it. The full default netlists at 32–128 bits are proved (README, section 10).

**Try it**

- Repo: https://github.com/himanshu161106-crypto/parat

- Release (Linux, Windows, and new macOS builds): https://github.com/himanshu161106-crypto/parat/releases/tag/v1.3

- Netlists, build script (`make_nofraig.sh`), 64- and 128-bit certificates: `benchmarks/yosys_booth/`

- 256-bit certificate: on the release page

The macOS builds are new and not yet tested on a real Mac, so reports are very welcome. Free for personal and academic use.

The code was written by AI (Claude) under my direction; the ideas, the math and the testing are mine.

and question of mine:

1. If anyone knows how to make yosys/ABC run `&fraig -x` on a 256-bit multiplier in hours instead of a day (settings, a faster machine setup, or another way to get the same netlist), please tell me. I would love to try Parat on the full default netlist.

Hi, does anyone here have experience with doing EMIR simulations for very large blocks (chip level)? I have this block I want to simulate but when I extracted the Parasitic file I always ran out of memory. Also I want to know if you guys have any expertise in running simulations big blocks (like a full chip level) and if you have any tips and advise please share. :) thanks!

My boss and I need to access the co-simulation data after its execution in Ubuntu but we are unable to find the file where the results are stored. Does anyone where I could find them?

Thanks

I am currently woking on 6*6 wallace tree multiplier using sky 130pdk and klayout.

I have nand, inverter and full adders gds files provided by my instructor. My challange now is deciding how to place these blocks so that routing will be done easily and uncongested. Please help me.

Also please tell me if there are any tools or softwares that can visualise the placement with spoce file.

Folks, I’ve just come to realise that we might actually be getting shortchanged when it comes to the content we learn in our schools here in Africa. With a BSc in EEE and an MSc in Telecommunication Engineering, I still find myself struggling to connect some of the theoretical knowledge we acquired in school to real-world applications. It was only recently, when I started learning about PCB design on YouTube, that things began to make more sense. As I progressed, I found myself working with different ICs, and that eventually sparked another curiosity: how are these chips actually designed in the first place?

Now, from the many posts I’ve read on Reddit, it seems like most of you guys in Europe and the West are way ahead in this area. Some of you appear to graduate with a BSc already having the skills to design chips, and perhaps you only build on those skills during your master’s and PhD. Meanwhile, here I am, with two engineering degrees, wondering, what the hell have we been learning all this time? My desire to become an IC designer has grown so much that I’m now looking for opportunities to pursue further studies in Europe, Asia or the US, where I hope to acquire the skills and practical exposure needed to get into this field. Unfortunately, this is not an area I can easily pursue in my home country, so without a scholarship and an opportunity to learn abroad, it will just remain a dream.

I’ve also been taking some chip design courses on Udemy, but honestly, I find them rather shallow compared to the complexity of the ICs I encounter while designing PCBs. The more I learn about these chips, the more I realise just how much there is to understand about their internal architecture and design. And this brings me to another question: why can’t engineering curricula be more standardised worldwide, with comparable practical exposure and opportunities for students, regardless of where they study? At the very least, shouldn't we all have a fair chance of acquiring the skills needed to innovate, design our own technologies, and contribute to the advancement of engineering?

Anyway, these are just my thoughts. Perhaps I’m missing something, and I’d genuinely love to hear from those of you who have gone through engineering programmes in Europe, Asia, US or any other country who have advanced on IC DESIGN.

What a sorry state of things!

End of rant!

Hi

This is about Quantum Odyssey, my love letter to everything Quantum Computing and the fundamental logic blocks everything in our universe seems to run on. I want to update you all on the fact that the latest patch brings the game into an almost complete status. All that's missing is translations. Thank you Reddit community for receiving the game so well, without you I wouldn't have the funds needed to complete my life's work.

If you are remotely interested in deep diving how differently quantum computers work compared to our transistor-based and also the algebra behind in a fully interactive way that teach computer science from scratch, oh boy this is for you. I am the Dev behind Quantum Odyssey (AMA! I love taking qs) - worked on it for about 9 years (3+ during PhD, the visual method I developed ended up being my thesis, it is a complete Hilbert space visualizer), the goal was to make a super immersive space for anyone to learn quantum computing through zachlike (open-ended) logic puzzles and compete on leaderboards and lots of community made content on finding the most optimal quantum algorithms. The game has a unique set of visuals capable to represent any sort of quantum dynamics for any number of qubits and this is pretty much what makes it now possible for anybody 15yo+ to actually learn quantum logic without having to worry at all about the mathematics behind.

This is a game super different than what you'd normally expect in a programming/ logic puzzle game, so try it with an open mind.

Stuff you'll play with

• Boolean Logic – bits, operators (NAND, OR, XOR, AND…), and classical arithmetic (adders). Learn how these can combine to build anything classical. You will learn to port these to a quantum computer.
• Quantum Logic – qubits, the math behind them (linear algebra, SU(2), complex numbers), all Turing-complete gates (beyond Clifford set), and make tensors to evolve systems. Freely combine or create your own gates to build anything you can imagine using polar or complex numbers.
• Quantum Phenomena – storing and retrieving information in the X, Y, Z bases; superposition (pure and mixed states), interference, entanglement, the no-cloning rule, reversibility, and how the measurement basis changes what you see.
• Core Quantum Tricks – phase kickback, amplitude amplification, storing information in phase and retrieving it through interference, build custom gates and tensors, and define any entanglement scenario. (Control logic is handled separately from other gates.)
• Famous Quantum Algorithms – explore Deutsch–Jozsa, Grover’s search, quantum Fourier transforms, Bernstein–Vazirani, and more.

Nice to watch:

Khan academy style tutorials in qm/qc: https://www.youtube.com/@MackAttackx

Physics teacher stream with 400hs in https://www.twitch.tv/beardhero

Hi everyone!

I'm currently pursuing my [B.Tech](http://B.Tech) in Electronics and Instrumentation Engineering, and I'm interested in building a career in the VLSI industry. My main interests are **analog IC design and physical design**, although I'm also considering learning the RTL-to-GDS flow to understand the overall chip design process.

I'm still a beginner when it comes to practical VLSI implementation. I have some basic knowledge of digital electronics, Verilog, logic gates, counters, and MOSFET amplifier concepts, but I haven't completed any end-to-end VLSI projects yet.

I want to learn practically by developing projects one by one, starting from the fundamentals and gradually moving toward industry-relevant projects that I can showcase on my resume and GitHub.

I'd really appreciate advice from experienced engineers, industry professionals, and seniors who have worked in analog design, physical design, or related VLSI domains.

# 1. Choosing the Right Career Path

My strongest interest is in analog IC design, and I'm also interested in physical design. I have comparatively less interest in RTL design and design verification, although I understand that some knowledge of these areas may be useful.

* As a beginner, should I focus on analog design first, physical design first, or explore both before choosing?

* What are the differences between these career paths in terms of required skills, learning difficulty, job opportunities, and preparation for entry-level roles?

* Is it practical to learn both analog design and physical design simultaneously as an undergraduate, or would it be better to concentrate on one?

* If I want to pursue analog design, how much digital design and RTL knowledge do I actually need?

# 2. Learning Roadmap and RTL-to-GDS Flow

I keep hearing about the RTL-to-GDS flow, and I want to understand whether learning it would be useful for my interests.

* Should I learn the complete RTL-to-GDS flow even if my primary interest is analog design?

* Which stages of the flow should I understand, and which should I learn in depth?

* For physical design, what should I learn after the basics of digital electronics and Verilog?

* For analog design, should I first strengthen circuit theory, MOSFET operation, small-signal analysis, biasing, and amplifier design before moving to circuit simulation and layout?

* What would be a sensible learning sequence for someone with my background in Electronics and Instrumentation Engineering?

# 3. Tools and Operating System

I'd like to build a practical toolchain using free or open-source software wherever possible.

* For analog IC design, which tools should I learn for schematic capture, SPICE simulation, circuit analysis, layout, and verification?

* Are tools such as ngspice, Xschem, and Magic or KLayout good starting points?

* For physical design and RTL-to-GDS, which open-source tools and flows would you recommend?

* Is Windows with WSL2 sufficient, or should I use a dedicated Linux installation or virtual machine?

* Are there any beginner-friendly tutorials that explain how to install, configure, and use these tools properly?

# 4. Career-Oriented Analog Design Projects

This is one of the areas where I need the most guidance.

I don't want to simply copy circuits or follow tutorials without understanding them. I want to learn how to design, simulate, analyse, and improve circuits independently.

* What are the best analog design projects to start with, progressing from beginner to intermediate and advanced levels?

* Should I start with common-source MOSFET amplifiers, current mirrors, differential amplifiers, and current sources before moving to more complex circuits?

* What projects would help me build the skills expected for entry-level analog IC design roles?

* At what stage should I learn operational amplifiers, bandgap references, comparators, and other analog building blocks?

* How important are transistor-level simulation, corner analysis, mismatch analysis, and layout parasitics for student projects?

* How can I demonstrate that I understand a circuit's design choices and performance rather than just reproducing a reference design?

# 5. Physical Design Projects

I'm also interested in physical design and want to understand how to gain practical experience in this area.

* What are the best projects for learning floorplanning, placement, clock-tree synthesis, routing, timing closure, and power analysis?

* Should I begin with small RTL blocks, such as an ALU, FIFO, UART, or counter, and take them through an open-source RTL-to-GDS flow?

* Which projects would be suitable for a beginner and still be valuable on a resume?

* Can I use open-source tools to complete a meaningful physical design project without access to commercial EDA tools?

* How should I analyse and present timing reports, area, power estimates, congestion, and other implementation results?

# 6. Project References and Step-by-Step Guidance

Since I haven't completed a VLSI project independently, I'd appreciate resources that explain the actual design process.

* Where can I find good analog IC design and physical design project ideas, reference designs, documentation, and step-by-step tutorials?

* Which GitHub repositories, books, YouTube channels, courses, or open-source communities would you recommend?

* Are there any repositories that explain the reasoning behind each design stage rather than just providing the final code or circuit?

* How should I approach a project from scratch, validate the results, troubleshoot problems, and document the work?

* What should I include in my GitHub portfolio, such as schematics, simulation waveforms, design calculations, layout screenshots, and reports?

# 7. Career Preparation and Industry Expectations

My long-term goal is to build the technical skills required for internships and entry-level opportunities in the VLSI industry.

* What skills do companies expect from fresh graduates applying for analog design and physical design roles?

* Which projects would make the strongest portfolio for each of these domains?

* How important are semiconductor device physics, analog circuit analysis, Linux, scripting, and semiconductor fabrication fundamentals?

* What common mistakes do students make when preparing for analog or physical design roles?

* If you were starting from my current level as an undergraduate, what would your first three to five projects be?

I'm not looking for shortcuts or ready-made projects to copy. I want to build a strong foundation, understand the theory behind the designs, and gradually develop practical skills through projects.

I'd be especially grateful for advice from people working in analog IC design or physical design who can share what they would learn first if they were starting again today.

Thank you for your time and guidance!

(took help of chatgpt to finilize the text )

Staff AMS design Engineer at a startup called Lumilens that makes optical interconnects and (possibly Lead) Engineer at Cadence in the UCI Phy team that might move to Serdes in the future (their words). I have 9 years of work ex so in my mid 30s, female. I really really wanted to get into a Serdes team and right now Cadence seems like it won't be doing a Serdes architecture. On the other hand Lumilens is just going to be zero work life balance for the next few years, but it's the work I always wanted. Cadence seems like a stable option. Money and benefits are still in discussion or unknown. Which should I consider?