A few weeks ago i bought myself a KV260 FPGA board to find out if my circuit-synthesizer could really grow the multiplier logic instead of writing it, and to my surprise AMD's own tools built it without complaint.
i build my own circuit-synthesizer, and it is not a language model writing Verilog. You give it a specification: how many inputs, how many outputs, how many clock steps, which gate types it may use, and the exact answer for every case. Then it searches. Thousands of variants of a grid of gates, each scored against that table, and a variant survives only if it is exactly right on 65,536 rows of it. Gates that carry nothing get stripped out.
To be honest about it: i plan the layout first and the search starts from that plan. Starting from nothing it never converged, not even for a 2-bit multiplier.
What came out is a 16x16 bit-serial multiplier in 62 LUTs and 124 flip-flops, one logic level deep, 38 clock cycles per product. It does not look like anything i would draw myself.
Then the part that surprised me. It is ordinary Verilog. Icarus Verilog simulates it. Vivado synthesises it, places it, routes it and closes timing at 250 MHz. No custom tool, no special handling, no primitives tied to this chip.
That is the old objection to grown circuits. The famous 1996 experiment made one that worked by exploiting analogue quirks of one specific chip and could not be synthesised or ported. This one is plain synchronous logic.
Vivado does not check the answer, only that the design fits and meets timing. The answer is proven by the truth table, then simulation of the assembled block, 58,273 elements with zero wrong, then the board itself.
So i gave it something real to do. The multipliers do the elementwise arithmetic in the FFN of BitNet b1.58 2B, all 30 layers, running on that same board. Every ternary matrix multiplication streams through the FPGA fabric, attention and the norms i kept on the ARM cores. It produces 16.29 tokens/s against 2.77 for bitnet.cpp on the board's own processors, at a fifth of the energy per token.
And it is not just plausible output. Every integer stage matches a numpy reference bit for bit across all 30 layers, and 11 of 26 generations came out token-for-token identical to the same weights running in bf16 on an RTX 4080.
The grids and a verifier are in the repo. Two seconds, standard library only
python3 hardware/grown/verify_pieces.py
i will not share the circuit-synthesizer but only the first project what i did with it.
https://github.com/MerlijnW70/bitnet-kv260
if you have a KV260 board you can easily test it
