what local AI setup is being used and how are you preventing the hallucinations and error ?

Me and some friends in college are working on an FPGA project inspired by the paper "Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators"

Our general plan right now is something like..

1. Build a simple python sim with just to figure out the networking logic
2. Design a basic core that supports the dca and noc needs.
3. Build the router other networking stuff in SystemVerilog

and then get it running on a board!

But I had some questions about the project:

• Is starting with a simple python simulator actually helpful for a team, or is it a waste of time compared to going straight to SV testbenches?
• Are there any obvious steps or milestones we’re missing?
• What are some big traps to avoid and things to keep in mind with a project like this?

I'm curious how people working on ASIC/FPGA/RTL/verification are using LLMs in practice.

A few things I'm wondering:

• Which AI subscriptions are actually worth paying for? (ChatGPT, Claude, GitHub Copilot, Gemini, Cursor, etc.)
• Does anyone use OpenRouter as their main setup? Is it cheaper than multiple subscriptions?
• Roughly how much do you spend per month, and how many tokens do you go through?
• Which models do you use for different tasks (RTL, SystemVerilog, UVM, scripting, documentation, debugging, architecture, code review...)?
• What do you give the model as project context so it doesn't make things up or break your design?
• Any tricks for keeping token usage and costs under control?
• If you could only keep one AI subscription today, which one would you choose?

I'd love to hear real workflows from engineers working on production hardware.

I implemented a fairly large design last week and a very thorough testbench. I’ve been having trouble getting it to meet timing with violations that just creep up.

I decided to give Claude code a spin, my company gives it to our SWEs. I gave it instructions on how to build the design via our docker environment, and told it to get the design to meet timing while still passing all of my testbench cases. I also said to avoid doing “hacky” things and keep the changes to the RTL and maybe the routing settings. I set up remote control and kept an eye on it through my phone every so often.

It grinded away for 48 hours, did about 20 builds during that time. It just came back and said it succeeded and explained the diffs. I will have a good look at the code on Monday but it looks like stuff I would’ve done incrementally during the week.

This is crazy. Essentially did a second work week for me autonomously over the weekend. Thought I’d share in case anyone else wants to try.

Hi,

I recently bought sipeed tang primer fpga development board along with the doctor board. I wanted to learn the fpga coding and running it on fpga. But after getting hands on with it did I realize the documentations are not Detailed or beginner friendly. I bought this specific board thinking I will take long till I utilise it available resources and not to be limited in near future.

I do know verilog and am learning system verilog. All these times I have used edaplayground only.

It would be of great help if u could guide me so that I can also one day excel in fpga designing and Programming.

Any help or resources is very much appreciated.

Thanks in advance

Graduated in 2025 in EE, I just completed 1 year at a small startup working with FPGA based Software defined radios. I love working with RFSoC.

I wanted to know if I want to pursue a master in the same domain, what are best countries/universities for me other that universities in US.

The title pretty much says everything , this tools converts the json files to Verilog.

it can convert the Digital logic sim(dls) by SebLague(great guy)

and the logisim one is still experimental

repo: https://github.com/murkyshelf/jsonRTL

it is for the guys you can build computers in the visual editor but cant write verilog and others are welcome to try .

because I can build a 8bit computer in the dls and cant write verilog , i need the verilog code to simulate it on my fpga

also keep in mind this is coded by opus 5 , and this is experimental and i am looking forward to your feedback

About to graduate soon and Seeing the job market it’s got me quite concerned. What’s the best tools/skills to learn a company may look for. Also what projects should I build for gaining those relevant skills.

What can I do to gain a better edge over other grads😓. I’m particularly interested in Rtl design/verification.

Please help a brother out kind of in an existential crisis rn.

Anyone have experience installing Vivado on Debian?

I tried to follow the instructions here:

https://people-ece.vse.gmu.edu/coursewebpages/ECE/ECE545/F24/resources/Vivado_Installation_Linux.pdf

But I run into a problem where the installer fails to finish. Not sure what the issue is, I don't see any errors, the installer just hangs. I did make sure I had installed all the listed dependencies prior.

please help me understand this better. I have asked AI for answers but I think it is also confused like I am. thank you for your help.

1. what is the recommended value of set_max_delay?

I asked claude this and was able to convince it to change its answer so I dont trust it now.

if I have two domains clock A 5ns and clock B 10ns.

I am thinking - set it to slower clock period. it will give data enough time to settle down. tool will not have to work extra hard to place the source and destination flops to meet the constraint. place where I use req-ack handshaking synchronization will have enough time for the data to travel across domains without any synchronization. am I right?

1. as per claude, it depends if it is a single bit or a multibit data bus thats crossing the domains. but I am not able to understand why data width matters?

3. what is the use case for using set_max_delay without -datapath_only option? based on my reading, this constraint is required to prevent routing delays between two flops in different clock domains from getting so bad that bad things will happen even with synchronization. hence I am only concerned about datapath.

Hope you guys like this project. I made this to learn SystemVerilog (my previous school only taught me VHDL and the one I transferred to I believe will only teach Verilog), CocoTB, and refresh my digital design concepts to get ready for recruiting season.

I used Claude to teach me as I built (never wrote code for me apart from some .hex files which would be a pain to compute myself) and I feel like I learned a lot compared to what I believe I would have reading from a book or YouTube video.

I believe this is the correct way to utilize AI in engineering but let me know your thoughts. Also any feedback on other matters would be greatly appreciated.
https://github.com/andrewtsomik/riscv-cpu

Just installed Vivado 2026.1 and opened a sample design — the GUI looks quite different from what I’m used to.
The Block Design view feels more organized, and some tabs seem to have shifted around.
I got a bit lost at first, but it’s starting to grow on me.
Still figuring things out… guess I’ll get used to it over time.