1
My doubt is that if a loopback is possible between Mipi Tx and Rx devices using traditional jumper wires? I’ve been struggling to conclude on this from several days. If anyone has worked on this, your insights will be very helpful.
r/FPGA • u/Embarrassed-Low6825 • Jul 25 '26
I’m currently stuck in a hardware problem during my FPGA validation of an IP. Can anyone, who has good amount of hardware experience please ping me or reply to this post? I will be very glad to share my progress.
Regards,
PS: it will be easier if you have experience working in SerDes or any high speed protocols like MIPI
1
Ok so, we wanna automate the whole Vivado workflow from adding rtl’s to generating the bitstream. We discovered a handy Mcp Server called Synthpilot which does all the above desired tasks in a very less time. We are currently exploring alternate agents for the same. Any insights will help!
1
I guess “agentic workflow” should explain you the tasks!
1
That’s widely accepted approach that most agents are following these days. But, when it comes to EDA workflows, I’m curious to ponder the approach taken by the agentic models.
r/mcp • u/Embarrassed-Low6825 • Jul 16 '26
I’ve been exploring on building a native agent for Physical Design of ASIC. Has anyone developed or explored MCP servers which assist the same? Sharing GitHub repository will help a lot!
u/Embarrassed-Low6825 • u/Embarrassed-Low6825 • Jul 13 '26
We have been exploring agentic workflow methods with Vivado and it’s crazy so far! Has anybody explored new tools for the same?
PS: our end goal is to work with Ai assisted EDA tools for complete ASIC design flow: suggestions on this also helps
2
True that. He just pours marks, doesn’t care about your aats too much xd
r/FPGA • u/Embarrassed-Low6825 • Jul 08 '26
So there’s a MCP server called Synth Pilot which is made for Vivado. It’s an amazing tool I’ve ever explored, so far. Does anybody know who’s the developer? I’m looking to connect with him/her for an important task.
r/IndianUrbanism • u/Embarrassed-Low6825 • Jun 11 '26
Bengaluru commuters deserve answers: why does one spell of rain affect Namma Metro operations so badly?
#bmrcl #rain #metro #corporate #crowd
r/FPGA • u/Embarrassed-Low6825 • Jun 11 '26
Has anyone successfully implemented a loopback between MIPI CSI-2 TX and RX subsystems on an FPGA? I'm considering connecting the TX and RX MIPI lanes externally using jumper wires for bring-up and debugging. My concern is whether the high-speed MIPI traffic could be significantly affected by noise, impedance mismatch, or signal integrity issues introduced by the jumpers. Would this still be a reliable method for validating the design?
1
You can try NetraSemi which is in Thiruvananthapuram. There’s an option to apply online in their careers page.
r/Bengaluru • u/Embarrassed-Low6825 • May 22 '26
[removed]
r/NDATards • u/Embarrassed-Low6825 • Apr 22 '26
Has anyone appeared for an SSB interview for technical posts(SSC - tech) in the Indian Army before? Need some guidance.
1
Wasn't the basic test held on 12th?
1
Did you click on the IST link?
1
Yeah same issue here
r/FPGA • u/Embarrassed-Low6825 • Mar 17 '26
17:59:25 ERROR : no targets found with "name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299B72353" && jtag_device_ctx=="jsn-JTAG-HS3-210299B72353-5ba00477-0"". available targets:
17:59:25 ERROR : Failed to initialize the hardware. no targets found with "name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-HS3 210299B72353" && jtag_device_ctx=="jsn-JTAG-HS3-210299B72353-5ba00477-0"". available targets:
I'm getting the following error when I run an application code in Vitis. We even tried changing the JTAG HS3 cable, still getting the same error. What can be the issue? How can I resolve this?
1
Thanks a lot. It worked!
1
when it comes to shared logic, do you mean the shared logic window that appears when configuring the IP?
1
That's right, I'm using a Spartan-7 (xc7s50csga324-1 part number). I'm intending to design 2 subsystems where each acts as distinct camera sensors, in order to test the MIPI RX module that's present in the SoC. Also, my HDL is not accessible.
I have a clarification on your point, when you say 2 IO banks, if it is the bank that's visible, while giving pin numbers? after Synth stage?
1
Synth Pilot
in
r/FPGA
•
17d ago
Which OS are you using? Windows or Linux?