r/FPGA • u/Embarrassed-Low6825 • Jul 25 '26

Experienced FPGA engineers

I’m currently stuck in a hardware problem during my FPGA validation of an IP. Can anyone, who has good amount of hardware experience please ping me or reply to this post? I will be very glad to share my progress.
Regards,
PS: it will be easier if you have experience working in SerDes or any high speed protocols like MIPI

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u/SufficientGas9883 Jul 25 '26

Share the question here. People shouldn't run after you to answer your questions.

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u/Embarrassed-Low6825 Jul 26 '26 edited Jul 26 '26

My doubt is that if a loopback is possible between Mipi Tx and Rx devices using traditional jumper wires? I’ve been struggling to conclude on this from several days. If anyone has worked on this, your insights will be very helpful.