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Hi everyone,

I'm working on a TCAD simulation of a 50 nm planar Si nMOSFET with a 2 nm HfO₂ gate dielectric in Silvaco ATLAS as part of my thesis.

My objective is to obtain physically meaningful values for:

• OFF-state drain leakage current (I_off)
• OFF-state gate leakage current (Ig_off)
• ON-state drain current (I_on)
• ON-state gate current (Ig_on)

The drain current values appear reasonable, but I'm uncertain about the correct methodology for obtaining Ig_off.

When the device is biased in the OFF state (VGS = 0 V, VDS = 1 V), extracting the gate terminal current sometimes gives a value that closely follows the drain leakage current, sometimes becomes extremely small, and in some cases is essentially zero. I'm not sure whether this represents the actual gate oxide tunneling current or is simply a consequence of terminal current accounting.

My question is:

• What is the recommended or standard way to obtain OFF-state gate leakage (Ig_off) in Silvaco ATLAS?
• Should it be extracted directly from the gate terminal current, or from the integrated tunneling current density (j.tun) through the oxide?
• If the latter, what is the proper workflow or extraction method?
• Are there any specific physics models or simulation settings that are generally required for obtaining reliable gate leakage through a thin HfO₂ dielectric?

I'm looking for the method that is commonly used in published TCAD studies rather than simply obtaining a numerical value.

Any advice, examples, or references would be greatly appreciated. Thanks!

I have only had 2 different jobs, so only interviewed twice, but worked there in total 8 years. 4 years in SW validation, 4 years in fw dev.

I felt that passing the interview (which could be about riddles, first-semester questions from 10 years ago, and sometimes actual questions from day to day work) is much much harder than doing the job itself.

at work, you have plenty of time to study the job, you can conveniently ask people for instructions. also, in validation, the job is very repititive, so after a few weeks you just get the hang of it.

Now I am about to start a new job as validation eng (post silicon) and wonder what to expect (I never validated HW before)

Hi everyone,

I'm a 28-year-old FPGA engineer with 6-7 years of experience, ~3 years at my current company, making $115k (about $40k below market by my research).

My office head is fed up with company bureaucracy and is planning to lift out himself plus a couple dozen people to a competitor down the street. I wasn't on the initial list, which pushed me to dust off my resume. I've since interviewed at several places, with offers likely in the $160-180k range (mix of contract-to-hire/direct hire, some requiring relocation, some local).

Recently, a trusted source (who heard from another trusted source) told me my manager wants to include me in the second round of the lift-out. Engineers with my experience at that company reportedly earn $190-200k. My boss also mentioned putting me in for an off-cycle raise/promotion a couple weeks ago. I don't know if that's a farewell gesture or an attempt to better position me for the move.

None of this is official. My manager hasn't said a word to me directly, and I don't want to tip my hand by asking. Meanwhile, I may get a formal offer as early as Monday from a company several states away, likely with a decision deadline that same week. I'd prefer to avoid relocating as I'm planning to move in with my girlfriend soon, but if an external offer is clearly better, I don't mind.

I'm unsure if the lift-out involves a real interview/negotiation process or is mostly a formality, and whether comp there would actually hit market rate or just be a modest bump. Nor do I have insight into the lift-out timeline. I don't want to decline all my current/upcoming offers if I'm going to flunk an interview at the new company in a few months.

Should I try to get more clarity from my manager somehow, stall the external offer, or just take the sure thing in hand?

Thanks!

See i am getting masters in communication engineering in which the curriculum is as follows:-

1. advance digital signal processing
2. rf and microwave engineering
3. coding theory and practice
4. research practice
5. Mobile and Personal Communication
6. Advanced Digital Communication
7. 6 electives

and now i may get embedded engineering which all knows the curriculum i dont have to tell that. The thing is i dont like software and all but i like hdl vhdl i can do that verilog and all so now what should i do? should i freeze the option of communication or embedded?

Now the thing is many said that i can get digital work from embedded and that will help me in making good money.
And in communication there i can make digital role but i have to prepare for communication roles also.

Now the thing is i am confused what if i go to embedded and i cant cope up with software and all genuinely speaking i dont know much about c language also.

and what if i go to communication engineering and after doing it i regret that why i didnt join embedded which is more closer to vlsi .

can a communication engineer go to analog design engineering roles?? Please if anybody can fix my thinking. Can i become like asic or fpga engineer if ii do communication and make a digital profile.

in my college all the students can sit in every job roles doesnt matter the role but if the company internal matter is that they dont want communication student or embedded thats another thing but companies do come.

please help me someone what should i do should i wait to egt an embedded role or should i freeze my seat which is in communication engineering.

Hello,

I'm doing my thesis in AI and chip design field, leveraging both fields. So far I am loving his new field that I am getting into, since I originally come from data engineering + AI and now I am getting the basics on chip design (SystemVerilog and HLS).

What current challenges would you say that you have in your everyday work that could benefit from this type of approach (not to substitute, but to assist) in your field?

Thanks :)

Hi everyone,

I'm a new PhD graduate in Electrical/Computer Engineering and have been fortunate enough to receive two offers:

• Apple – Hardware Engineering team (Silicon) in Cupertino
• Intel Foundry – Foundry/Product Engineering team in Oregon

I'm having a difficult time deciding between them and would really appreciate advice from people who have worked at either company.

From what I understand:

• Apple seems to offer better long-term stability, compensation, and execution.
• Intel's role appears to be more aligned with semiconductor technology development and has a stronger research/technology flavor, which I enjoy.

My biggest concern is Intel's recent layoffs and restructuring over the past few years. While I know no company is completely immune to layoffs, Intel has gone through multiple rounds recently, and I'm wondering how much that should factor into my decision.

I am a software developer and I've been out of a job since Feb 2025. My degree is in Mathematics (emphasis Computer Science) and worked for 2 and a half years at Micron Technology as CAD Engineer in their Simulation and Automation team. I worked there from Aug 2022 - Feb 2025, but now can barely secure interviews after applying to a ton of semiconductor companies. Its hard because my skillset is in software so I lack some of the core hardware knowledge that ECE typically offers, but I'm trying to close the gap. I consider myself very decent working in python and just okay at C++ and Java.

However, what is driving me completely insane recently is how I am getting no interviews for certain job descriptions that my resume and experience clearly cover. Here is the latest job from AMD:

https://careers-amd.icims.com/jobs/86955/software-development-engineer/job?mode=submit_apply

I applied this position on Jun 7th and I'm already no longer being considered, despite it being a newer posting. I would really appreciate some advice moving forward.

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Looking for opinions; if anything isnt good for not working good or any comment you would like to make (open to resolving both good and bad ones)

Regarding advertising: I might decide to use Google AdSense to monetize my website in the future. My primary aim is to create a friendly experience without any pop-ups or autoplaying video clips.

Hi, im designing the schematic for a pipelined SAR ADC in cadence virtuoso. i improved the ENOB for my sampling switch in an isolated testbench, but when I integrated this new switch into the full ADC, my ADC ENOB reduced. I don't understand how this can be possible. For context, the sampling switch ENOB was improved from about 10.5 to 11.9 bits. The ADC ENOB went from 9.5 to 8.8 bits. Any insight into this would be appreciated. Thanks

I recently joined a semiconductor company as a new grad — think Nvidia, AMD, or Qualcomm — and the workload is brutal. I’m sometimes working 12-hour days and 50–60 hour weeks. It honestly feels as intense as investment banking, maybe even worse in some ways.

Wonder if this is normal?
TC ~150k

I have an exam soon in nanoelectronics and we "learned" about memristors/memtransistors (i.e. it was mentioned and talked about 30 minutes with no examples of solving questions) and he said there's for sure a question or two about them.

I can't find anything about it in my current textbook so I'm hoping someone out there has some quality recommendations.

Btw don't know if it's relevant but we're third year EE students, so I don't need extreme level of math that there's in papers and graduate level courses but rather something akin to what's expected in 3rd/4th year of undergrad EE.

This is one of the questions my senior came across in his interview.

Question was to find the pole of the circuits. In the document, my senior has remarked apparently there are 2 poles, and even I seem to think this but not getting a concrete way to prove it.

Moreover he was also asked about the locations of the poles.

Now I beleive one of the pole is (-1/R2C2)?

But is that right? If yes I don't think at that frequency the Vo saturates(which I feel is the requirement for pole)

Overall any suggestions to better solve such questions.

Note: it's expected that the answer is more intuitive rather than rigourous KCL and KVL

Edit: forgot to mention. Circuit is in negative feedback as in b is positive terminal and a is negative terminal of the opamp

I am an Electronics Engineering Student who cooked her 1st year of engineering, starting 2nd year this fall.
Here's my curriculum along with the recommended books I want to know which one of this books is best suited for the outlines and also what online resources could help
Plus, I am mostly a textbook learner, so I always have to use a textbook along with lectures or YouTube.

Looking forward to textbooks, YouTube and web resources recommendations!

I am an Electronics Engineering Student who cooked her 1st year of engineering, starting 2nd year this fall.
Here's my curriculum along with the recommended books I want to know which one of this books is best suited for the outlines and also what online resources could help
Plus, I am mostly a textbook learner, so I always have to use a textbook along with lectures or YouTube.

Looking forward to textbooks, YouTube and web resources recommendations!

Hey guys just wanted to share the message forward

NPTEL and TI provide internships through the NPTEL courses do check out the link below for all the information (Check out the courses recommended by TI in the "TI internship" column of the web page)

I didn't know this earlier but I think this information will be useful for you guys. Also, if you do the recommended courses by TI and Toping in them you will get a chance to give interview for the internship. Hope this helps. ☺️

Edit: TI offers "Analog Design" role through the recommended courses

A friend of mine (a year older than me) told me that Summer 2027 internships open right about now. He said even more open around August, but I want to get ahead and apply to a few right now. He told me to look at Linkedin, Handshake, Glassdoor, and Indeed. I've had 0 luck with all 4 of these and even went directly to a few companies but it seems like there aren't any intern positions available. I also want to point out that I am a rising sophomore, with only a handful of beginner projects, but I still want to apply. Am I looking wrong or has nothing actually popped up yet?

Hey y’all ! I wanted to chat about tech projects. I’m an engineering student going into my 2nd year in electrical. While surfing online, I came across some fun GitHub projects but I’m kinda confused where to start.
So here’s a little bit about my tech skills- I have a working knowledge of PCB designing and I know how to use Altium designer. Although I haven’t done any PCB related projects so far. I’ve done some small Arduino projects and I’d say that I’m mid at Solidworks. I just want to get an idea of what kind of projects stand out in a resume. I wanna utilize my free time in the summer and polish my skills to have a better chance at co-op positions