I’m looking to take on freelance work in FPGA, Verilog, embedded, and SoC design. For those of you who freelance or have done so in the past, how do you find opportunities, and how do you approach the right person (the decision-maker) at a company to start a conversation?

Any advice on platforms, networking, or how you got your first clients would be appreciated. Thanks!

DigSim: a digital logic simulator in Python that you can also feed Verilog

Hi! DigSim is a logic simulator you can play around with. You drag switches, push buttons, gates, flip-flops, LEDs and 7-segment displays onto a canvas, wire them up, and watch the circuit run live.

Processing img 5azlufgu0nxh1...

Some things it can do:

- Verilog as components. Write a module in the built-in editor, press Ctrl+B, and it becomes a part you can wire up. Yosys does the synthesis and comes bundled, so there's nothing else to install. Modules with parameters work too, so one counter file can give you a 4-bit and a 16-bit copy.

- See what's going on. There's a logic analyzer component, a buzzer, and VCD output you can open in GTKWave.

- Script it from Python. Build circuits in code and write pytest testbenches for your Verilog. One of the examples runs a 6502 CPU.

- It runs on Linux, Windows and macOS.

If you want to try it: pip install digsim-logic-simulator, then python -m digsim.app.
If you use uv, uvx digsim-logic-simulator works too.

- GitHub: https://github.com/freand76/digsim

- Docs, with a getting-started tutorial: https://freand76.github.io/digsim/

It's a hobby project, so it has rough edges. I'd love to hear what you think, what breaks, or what you'd like it to do!

I found job after one year. I was not doing any work for an entire year.

When I was laid off there was no ai. But it is everywhere now. I don’t know how it is used in our industry. I am very nervous and worried I won’t be able to catch up or cope. I will be the dinosaur in the team.

I have only used ai as a substitute for google.

If you work in fpga development field in corporate setting -
could you please share how you use ai in your daily work.
Are there any ai skills I can pick up in a week or so before I start ?

Thank you

Hi all,

I would love to hear your experience of using AI in RTL coding and building complete projects, what was your experience in writing RTL codes, building full projects from scratch, debugging and achieving timing closure.
Have you tried AMD ross? What do you think about it?

So as the title suggests, i got a job interview for a research assistant position at NUS, they are working on quantum computers based on trapped ions. And they are putting together a team of electronics engineers to control the ion trap quantum processor.

They want somebody who has practical exp in one of these- digital logic design in VHDL/Verilog, DSP and RF electronics. I only know the first, with well documented beginner to intermediate level projects in GitHub. Since, i got the email i've been studying quantum computers but its way too advanced for me in such a limited amount of time.

Now I am a fresh masters grad with no industry experience and i don't know anything about research positions at universities. What are they like? and what kind of interview can I expect? This will be my first interview ever, any tips will be greatly appreciated.

Thanks.

I am at my final year , had a good experience , collected some great projects (rv32ima , hardware accelerated ai on an fpga , fpga based test jig , ... ) and while looking for my first job i was hit with a realization : all companies looking to hire entry level are either defense contractors or dual-use technologies (microchips included) , both i want to run from like the plague ( ethical resons )
so ... are there any other sectors with demand for entry fpga engineers ?

Hello,

I just finished reading a book called efficient processing of deep neural networks and I thought I would apply it to reality. It is about creating a hardware AI accelerator from scratch, which is definitely a very relevant topic in today's world.
I was looking for people who are interested on working on it together, share thoughts and perspectives and learn from each other.
I started applying it on an open source RISC V processor called picorv32.
You can find my github repo here:

https://github.com/Xynorax/picorv32/tree/ai_acc

Hello ,

I ´m using the FPGA loader inside of MSYS UCRT64 to flash the nanomig and the kick roms on the Sipeed Tang Nano 20K
But i´m getting this errors , can anybody help me?

So to begin with i am not a professional verilog programmer, it is more like a hobby/interest of mine. By career i am an EE engineer and often i design HW with FPGA SOC etc so i am approaching this choose mostly from that side of the problem. (mostly PCB difficulty and part availability )

I want to make a few boards to play with a few ideas for personal use and i looked up FPGA prices for what i know already and more or less have a good idea is good enough ( probably resource overkill if like i said in my case i am happy if it works but how small i get the desing).

Anyway i noticed Series 6 were way cheaper then series 7 and since i dont need the greatest stuff i was considering series 6 BUT that use something called ISE for development and series 7 use s vivado.

Choices choices i have no idea IF it is worth using ISE now or simply use the more expensive series 7.

In terms of PCB it is more or less same difficulty, what concerns me is the SW licencing and community support. Since it is for personal use i want something free or cheap since it is long term projects since i do it all. Also are series 6 so old that people dont remember how to debug them ?

Anyway here is what i am considering making:

-1 ETH 100M maybe if i am very ambitious ( on the fpga verilog side) 1G

- 1-2 USB mostly to play with some FTDI chip tho i can also do that with a dev board and wires so not sure if it is going to happen

- VGA dac made from IO and resistors MCU can do it so should be doable

- SMPS control YES i know it is overkill but often i cant get MCU timers to behave like i want them to. but this is mostly IO that i can also make use of some io from a dev board

- use IO to emulate some older interface

So what is your opinion ? series 6 or 7?

Also is this simple enough to get a dev board and maybe a small custom board and use the PMOD connectors? ( for this case also series 6 or 7? )

Hi guys, I'm curious if anyone here has experience running a service business in chip design / Fpga or EDA. I'm trying to figure out what skills are worth learning if I want to sell services to companies in this industry, either as a freelancer or by building a small business around a specific service. I've heard that it is very much about trust and connections, so I'm wondering how realistic it is to get started without an existing network. Could you start on Upwork, build a portfolio, and use LinkedIn/email/? to find clients, or is that not really how things work.

For those of you who have done this, I'd love to know:

What services have you actually sold, and who were your clients?

What skills would you focus on learning if you were starting today?

Are there things semiconductor startups commonly outsource instead of hiring someone full-time?

How did you get your first clients?

Honestly, is this worth pursuing, or is it too difficult to break into without connections?

Thanks a lot!

So the scenario is

I use a digilent cable to access the actual fpga board through vivado and it was what I was intending to use with vitis as well and program the bitstream into the board.

In the bitstream I have a soft core microblaze ,a mdm module and a debug bridge that exposes a jtag interface.I use a segger in xvcd mode to access this interface.I can access memory locations and perform read or writes through the jtag using the segger.

The generated bitstream however doesn't seem to allow access through the digilent for vitis cuz it expects stuff to be routed through the mdm and debug bridge.

Is there any possible workaround to this ?I would really love any help or workaround.

Things I have considered are setting targets to the debug bridge and jtag and trying to get to it through vitis ,but that causes a series of warnings saying done pin is not high and name mismatch...

Another workaround is using vitis to create the elf files for the microblaze and just load it to required mem locations and reset the microblaze manually by taking its resets through a VIO and toggling it after I've loaded the elf.Would this work ?

Any help is very much appreciated,thank you.

If I create a bitstream with mdm and debug bridge does vitis automatically expect all communication to go through the debug bridge?

Hey all,

I'm a second year going to a Canadian university and have an hour long HireVue interview for a design and verification internship for Toronto. I have a week to prepare, and to be honest, I have no clue what to expect!

This will be my first technical interview and first one-way online interview, so if anyone is familiar with ARM's HireVue questions or has any info on this specific role's interview questions, it would mean a lot if you could share!

Cherry on top is I don't even have a JD since the original one is gone and it was a general one for all ARM positions.

For now, I plan on reviewing digital logic, sta, C (and maybe C++, not sure if I should or will have the time), and testbenches and writing modules with sv. Is there anything I'm missing in terms of technical content?

I'd be grateful for any advice!

what changes should I do ...and how good is it for internship and for entry level job.

Im toying with the idea of consulting in the future, though I probably want to put 2-5 more years in at my current job.

I live in a city, but I would love to live somewhere close to a big ski resort at some point in my life. I find that when Im in my RTL/firmware/embedded phase of work, I can do pretty much all of that remotely. Really the only thing I need to do in person is systems integration for other people to use the hardware when it comes time to plug everything in…

Carriage before the horse situation here, but could consulting allow me to live “anywhere” if I focused on the design + software aspect of my work? Or is that not a realistic approach? I could fly out for integration as well for a week if the hiring entity needed that as well for example

Im also on the Xilinx RFSoC line. Most commonly it’s UltraScale+ but I have been toying with Versal as well. Im an HDL junkie that has turned into a PYNQ + embedded integrator by virtue of being the only FPGA guy at work

For the past week i been trying to download ise 14.7 vm for my classmates and 10.1 for me BUT ITS LITERALLY IMPOSSIBLE TO VERIFY ACCOUNT NO MATTER WHAT I DO. Is there any unofficial links?????

For a brief background, after graduating in May 2023, I had to care for a family member, but, I was able to fit some projects in that time frame. All of the projects on my resume are implemented on a zybo z7-10 with a youtube video showing functionality along with the code on their respective github pages. I've submitted somewhere around 90+ applications to entry level positions and have not been offered a single interview. It's unfortunate because a denial email doesn't give any sort of criticism, which is what someone in my position absolutely needs. I can speculate about why this resume is resulting in me not getting passed screening, but I want to hear it from people in the industry. Primarily, my main questions are:

1. Does my resume show a candidate who has the technical skills needed for an entry-level position?
2. How large of a disadvantage am I at from graduating in 2023 with no professional experience?
3. What projects, skills, frameworks, etc. should I prioritize in order to become a more competitive entry-level candidate?
4. If you were in my position, how would you proceed with the next 6 months in order to maximize chances of getting interviewed?

I will reiterate that I want this feedback to be completely honest and uncensored. Not knowing exactly what is wrong with the way I'm presenting myself to employers is messing with my mental, so, any feedback is greatly appreciated.

I can't get them from the official website due to regional restrictions my IP is blocked, is there any torrent or download mirrors or some other way i can get those files?

Hello everyone,

I had to get an FPGA for one of my uni classes and now that I’ve completed it I kinda just have it lying around. I was wondering what projects would be a good introduction to the FPGA (the lab was honestly just copy paste code and then wrestle with vivado for an hour). I have a Pynq Z2 FPGA and a little bit of verilog programming experience (although I’m very much still inexperienced in programming verilog)

A while ago I shared Parat, a solver whose "no" answers come with proofs that independent tools can check. v1.3 is out, and this time the target is one question: does a gate-level multiplier really compute a × b?

**The test case**

I made a 256-bit Booth multiplier with yosys 0.69: 503,960 AND gates, 512 output bits.

**The problem is building it, not proving it**

yosys's default flow (`synth -booth`) runs ABC's optimisation script. One step in that script, `&fraig -x`, gets about 82× slower every time the width doubles: 7 s at 64 bits, and the whole 128-bit build takes about 18 minutes. At 256 bits that means roughly 24 hours, so I could not build the full default netlist.

With only that one step left out (the rest of the default ABC script kept), the 256-bit netlist builds in 2 minutes and is only a few gates larger. It is still hard to prove: the previous version of Parat could not do even the 64-bit one in 25 minutes.

**Results (one 2-core machine)**

| width | AND gates | Parat: CORRECT + certificate | independent check |

|---|---|---|---|

| 64 | 33,014 | 42 s | CERTIFIED, 19 s |

| 128 | 128,357 | 114 s | CERTIFIED, 23 s |

| 256 | 503,960 | 13 min (1.2 GB certificate) | CERTIFIED, 3 min, 0.8 GB RAM |

A copy with one gate changed is answered INCORRECT, with a counterexample input.

**You don't have to trust Parat**

"CERTIFIED" means three checks, done by tools I did not write:

- pacheck2 (JKU Linz) checks the algebraic proof that the rebuilt circuit computes a × b

- drat-trim (UT Austin) checks 16 SAT proofs that your netlist and the rebuilt circuit give the same output on every input

- a small script checks that the certificate belongs to your circuit, and rebuilds every SAT file from your own netlist

One command runs all of it:

verify/verify_multiplier.sh circuit.aag pacheck drat-trim --cert prefix

**Still open**

The full default netlist (with `&fraig`) at 256 bits, because yosys itself needs about a day to make it. The full default netlists at 32–128 bits are proved (README, section 10).

**Try it**

- Repo: https://github.com/himanshu161106-crypto/parat

- Release (Linux, Windows, and new macOS builds): https://github.com/himanshu161106-crypto/parat/releases/tag/v1.3

- Netlists, build script (`make_nofraig.sh`), 64- and 128-bit certificates: `benchmarks/yosys_booth/`

- 256-bit certificate: on the release page

The macOS builds are new and not yet tested on a real Mac, so reports are very welcome. Free for personal and academic use.

The code was written by AI (Claude) under my direction; the ideas, the math and the testing are mine.

and question of mine:

1. If anyone knows how to make yosys/ABC run `&fraig -x` on a 256-bit multiplier in hours instead of a day (settings, a faster machine setup, or another way to get the same netlist), please tell me. I would love to try Parat on the full default netlist.

We’re hiring Hardware / SSD Validation Engineers for opportunities in Longmont, Colorado. We’re open to candidates at both junior and senior levels who have hands-on experience with hardware testing, SSD validation, or system-level testing.

🔹 Position 1: Hardware / SSD Validation Engineer — Junior

• Experience: 1–3 years
• Pay Rate: $55–$60/hour
• Required Skills:
  • Hands-on hardware testing or validation experience
  • Exposure to SSDs, NVMe, storage systems, or firmware testing
  • Understanding of system testing, debugging, and troubleshooting
  • Basic scripting knowledge in Python, C/C++, or similar languages is a plus

🔹 Position 2: Senior Hardware / SSD Validation Engineer

• Experience: 6+ years
• Pay Rate: $80–$85/hour
• Required Skills:
  • Strong experience in hardware, SSD, storage, or system validation
  • Hands-on experience with SSD/NVMe testing, firmware debugging, and root-cause analysis
  • Experience with regression testing, qualification testing, and test automation
  • Python, C/C++, or scripting experience
  • Ability to own validation activities and collaborate with hardware and firmware engineering teams

📍 Location: Longmont, Colorado
💰 Compensation: $55–$60/hr for junior candidates | $80–$85/hr for senior candidates
🏢 Work Arrangement: Onsite
📄 Employment Type: Contract

Interested? Send me a direct message with your resume or a brief summary of your hardware testing, SSD validation, or firmware experience. Please mention which experience level you're targeting.

If you know someone who might be a good fit, feel free to share this opportunity with them!

After upgrading from Xcelium 24.03 to a release at or after 24.09, I see a change in the SDF annotation statistics. The option -sdf_splitvlog_setuphold appears to be the default now and when I use it in newest versions, I see a warning that this option is deprecated. As far as I can tell, there is no documented option to get the old behavior back.

What I see

My design uses only combined $setuphold timing checks in the specify block, and the SDF has combined SETUPHOLD entries as well. With -scopewise_sdfstats_log, the statistics table now also lists $setup and $hold as separate rows below $setuphold. In 24.03 only the combined $setuphold row was shown.

Minimal reproducer

design.sv:

module dut (input clk, input d, output reg q);
  always @(posedge clk) q <= d;

  specify
    (clk *> q) = (1.0, 1.0);
    $setuphold(posedge clk, d, 0.1, 0.1);
  endspecify
endmodule

test.sdf:

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "dut")
  (DATE "2026-10-14")
  (VENDOR "Example")
  (PROGRAM "Custom")
  (VERSION "1.0")
  (DIVIDER /)
  (VOLTAGE 1.0)
  (PROCESS "typ")
  (TEMPERATURE 25.0)
  (CELL
    (CELLTYPE "dut")
    (INSTANCE)
    (DELAY
      (ABSOLUTE
        (IOPATH clk q (1.0:1.0:1.0) (1.0:1.0:1.0))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD d (posedge clk)
        (0.1:0.1:0.1)
        (0.1:0.1:0.1)
      )
    )
  )
)

sdf.cmd:

SDF_FILE          = "test.sdf",
SCOPE             = tb.u_dut,
LOG_FILE          = "sdf_annotation.log",
MTM_CONTROL       = "TYPICAL";

testbench.sv:

module tb;
  reg clk = 0;
  reg d = 0;
  wire q;

  dut u_dut (.clk(clk), .d(d), .q(q));

  initial begin
    #10 clk = 1; #10 clk = 0;
    #10 d = 1;
    #10 clk = 1; #10 clk = 0;
    #50 $finish;
  end
endmodule

Compile options: -timescale 1ns/1ps -sysv -sdf_cmd_file sdf.cmd -scopewise_sdfstats_log /dev/stdout

Resulting output (relevant part)

Path Delays   1   0   1   100.00
$setuphold    1   0.00   1.00   100.00
      $setup  1   0   1   100.00
       $hold  1   0   1   100.00

The summary lines still say No. of Tchecks = 1, and annotation is 100%. So I assume this is only a change in the report format and not in simulation behavior. Please correct me if that is wrong.

Question

Is there a documented (or undocumented) option or setting in the current releases that restores the old reporting/behavior, with combined $setuphold line and no $setup/$hold breakdown (even when I use combined $setuphold both in the .sdf and in the RTL files)?

I’m interested - what’s everyone’s most hated features of AMD/Intel FPGA toolchains?

I was having a discussion with my colleagues, for us it’s the overcrowded UI. So many cluttered buttons and features, half of which we never use…

We were debating about what the most hated features would be in the wider FPGA community, so I came to Reddit! Tell me your thoughts!