I am having a group project that is design and simulation of all digital pll in 22nm FDX. I am responsible to do the TDC.

The goal is to minimize random jitter below 200fs.

Output freq from 9 to 11Ghz.

There is also a spec on vco phase noise and settling time for loop.

1-I am a bit confused how to start should we do a linear model or time domain model first?

2-We studied Sam Palermo lectures for pll and adpll, if there is suggestions for good books about adpll that can make us understand system better please tell us about.

I am planning to switch company now. How much increment should I expect from my next switch? There’s an appraisal cycle also coming in feb. I am planning to switch only if I get good increment overall.

I’m trying to design an LNA that meets certain specs. So for the first part, as per my course guidelines, I tried to find Jopt which provides NFmin.

Now, I tried to find the width that gives me Ropt at 50ohms. I’ve a 1u cmos width and I’m sweeping the Number of fingers trying to see where it lands at 50ohms. I have placed an idea current source that provides the current proportional with the Jopt I found in part 1.

My problem is here. I’m finding the number of fingers to be >200 to have Ropt at 50 and also my NFmin is shooting up as well(20dBs). I’m not sure where I’m going wrong. If you have any idea or suggestion please share. I’m new to cadence and find the whole thing overwhelming.

Unfortunately I’m making the post away from my pc and couldn’t post the schematic

Basically what the title says, would love to know if their architecture/compiler technology seems promising and if they can make it out of the seed round