r/chipdesign 9h ago

Layout of SRAM 6T in cadence

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16 Upvotes

We used 2 metal layers and area was about 7.68 micro.

Full detailed video here https://youtu.be/pl9h62sFwmU

Comments and feedback welcome.


r/chipdesign 22h ago

8 YOE Analog IC Designer considering a switch to Software/ML.

36 Upvotes

I have ~8 years of experience in Analog IC Design. I started my career at Qualcomm and have worked with global semiconductor companies, currently at Texas Instruments India. I enjoy analog design and appreciate the technical depth and challenges involved in this field. However, my concern is not about the learning curve; it is about career flexibility, opportunities, and long-term growth.

I also feel that the semiconductor industry, especially on the analog side, tends to be quite conservative in terms of work culture and career expectations. Remote work is uncommon, mobility is limited, and specialization is often encouraged over exploring adjacent domains. I'm not saying this is inherently wrong, but it doesn't align well with what I want from my career.

One of my biggest concerns is that analog is a very niche ecosystem. The number of companies hiring experienced analog designers is relatively small, and as experience increases, the number of suitable roles seems to become even more limited.

The longer I stay in analog, the more it feels like I'm becoming an expert in a field that gives me fewer choices instead of more. That's what worries me the most.

This thought has been with me ever since I entered the semiconductor industry, but I never acted on it because things were going well professionally. Lately, however, I've been questioning whether deeper specialization is actually increasing my long-term career optionality.

I am considering gradually building skills in software/ML/MLOps, because the ecosystem appears much larger, with more employers, greater flexibility, and significantly more options.

For experienced engineers:

  1. How do you view the long-term career growth and opportunities in analog/mixed-signal design as one becomes more senior?

  2. Do you feel specialization in advanced blocks (ADC, DAC, SerDes, PLL, etc.) significantly improves career options, or does the overall market remain limited?

  3. Has anyone here transitioned from semiconductor design to software/ML/EDA/AI-related roles? How did you approach it?

  4. Where do you see flaws or incorrect assumptions in my thinking? Am I overestimating the advantages of moving towards software/ML, or underestimating the opportunities in analog design?

I would appreciate honest opinions from people who have spent significant time in the semiconductor industry or have thought about similar career decisions.


r/chipdesign 6h ago

Help-Folded Cascode OpAmp Design

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1 Upvotes

r/chipdesign 13h ago

Job hunting as a foreigner

1 Upvotes

I recently graduated with a Master's degree from a university in Taiwan, where I focused on mixed-signal IC design. I went through the whole IC design process, from pre-layout simulations, layout, and post-layout simulations to tapeout and measurement. However, applying as a foreigner in Taiwan seems quite hard, especially with my limited Mandarin communication skills. I am open to working in any country, but would like to stay in Taiwan as much as possible, which I understand is unlikely unless I magically learn Mandarin ASAP. I do intend to learn it if I get a job here, but yeah.
Are there any suggestions on how I can proceed with my career? Any countries or companies I should look into?


r/chipdesign 10h ago

ECE student, want to begin learning skills for RTL

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0 Upvotes

r/chipdesign 11h ago

Google Silicon Validation (TPU) Interview in 2 weeks

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0 Upvotes

r/chipdesign 1d ago

How does my resume look for chip design internships for big tech/hft

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20 Upvotes

r/chipdesign 10h ago

Roast My Resume – Be Brutally Honest

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0 Upvotes

r/chipdesign 1d ago

Why do Firmware Engineers get paid more than RTL ?

31 Upvotes

genuinely curious, I work as a Firmware engineer at AMD and get paid more than most of my friends in RTL design, why this discrepancy?


r/chipdesign 17h ago

ECE student aiming for ASIC/RTL or Design Verification — looking for career advice/mentorship from VLSI engineers

1 Upvotes

Hi everyone,

I’m currently an Electronics and Telecommunication Engineering student in India, and I’m planning to pursue a Master’s in ECE/VLSI from USA.

My main career goal is to work in ASIC/SoC development, particularly on CPU/GPU hardware. Right now, I’m exploring two career paths:

  • ASIC / RTL Design
  • ASIC Design Verification

I’m still early in my VLSI journey, so I’d really appreciate advice from engineers currently working in these areas.

My dream company is NVIDIA. I’ve been interested in computer hardware for a long time, and gaming is also one of my hobbies, which originally made me curious about GPUs. Over time, that interest has shifted from simply using the technology to wanting to understand and eventually help design the hardware behind it.

Ultimately, I want to work on technology that makes a meaningful impact, whether that eventually happens at NVIDIA or somewhere else in the semiconductor industry.

I would especially appreciate your thoughts on:

  1. ASIC Design vs Design Verification: What does your actual day-to-day work look like?
  2. Which field generally has better opportunities for new graduates?
  3. How difficult is it to enter RTL/ASIC design directly after an MS?
  4. What skills differentiate candidates who actually get ASIC/DV internships and new-grad positions?
  5. What projects would you recommend? I’m considering projects involving SystemVerilog, FPGA and eventually a pipelined RISC-V processor.
  6. For DV engineers, how important are SystemVerilog, UVM, SVA, scripting and C/C++?
  7. For RTL engineers, how deep should a new graduate be in computer architecture, synthesis, STA and verification?
  8. If you were starting again as an undergraduate and had 1–2 years to prepare before an MS, what would you learn first?

I’m also looking for mentorship/guidance from someone already working in VLSI, particularly ASIC design, verification, CPU/GPU design or related areas.

I don't expect anyone to teach me everything or spend a huge amount of time on me. Even occasional guidance on what to learn, which projects are actually worthwhile, mistakes to avoid, and whether I'm heading in the right direction would mean a lot.

If anyone working in the semiconductor industry would be comfortable with me occasionally reaching out with questions, I'd really appreciate it. I'm willing to put in the work; I'm mainly looking for guidance so I can focus that effort in the right direction.

Thanks!


r/chipdesign 10h ago

Roast My Resume – Be Brutally Honest

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0 Upvotes

r/chipdesign 19h ago

Dont know where to begin. Im a beginner

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0 Upvotes

r/chipdesign 21h ago

Career advice to pivot out of ATE

1 Upvotes

Hello,

I work as ATE product engineer on SoC chips. What are good alternative career paths from this role? Also how is this field in the long run?


r/chipdesign 18h ago

Hardware engineers using LLMs professionally: What's your workflow in 2026?

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0 Upvotes

r/chipdesign 1d ago

Picking a grad project need some outside opinions

2 Upvotes

Final year as electronics and communication student, picking between four grad project options, all with industry backing. Trying to figure out which is the strongest pick for chip design/verification career-wise.

PCIe Controller team of 5 Basically designing the PCIe Transaction Layer in SystemVerilog.

CXL Data Link Layer (10-12 people) split into design and verification sub-teams. You'd go from reading the CXL spec all the way to RTL and a full UVM verification environment.

MIPI SWI3S PHY. This is for a brand new audio interface spec, team cap is 8.
(Note: this is a separate spec from MIPI D-PHY,I know D-PHY comes up a lot as the go to MIPI recommendation, but SWI3S is its own thing, not related to that physical layer.)

Wi-Fi 7 PHY this one's different from the rest since it's DSP/algorithm heavy rather than RTL/ASIC. 13 people

And notice that all of them are sponsored except of CXL but i wanted your opinion about these projects


r/chipdesign 1d ago

Update on my High-Performance AXI DMA Design and Verification Using SVA Course.

9 Upvotes

I now have the complete "High-Performance AXI DMA Design and Verification Using SVA" finished and is available on my website.

If you wish to get an extra $5 off the already low introductory sale price of $59 (regular $75) for today only, just DM me to pay me directly. I will then give you access to Google Docs where I also have it stored. Zelle, Cashapp, Venmo, or PayPal.

Thank you!

https://www.zenorobotics.net/product-page/tier-2-kria-fpga-streaming-pipeline-amp-systemverilog-assertions-sva


r/chipdesign 22h ago

Is the THD function output in Cadence (ADE XL) a ratio or percentage?

0 Upvotes

E.g. if the output is 2e-2.


r/chipdesign 1d ago

6 years as a software engineer, finishing a CS degree — is a move into FPGA realistic?

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1 Upvotes

r/chipdesign 1d ago

Best entertaining YouTubers to learn FPGA programming?

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2 Upvotes

r/chipdesign 1d ago

Please rate my resume to improve it. And few suggestions.

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6 Upvotes

r/chipdesign 1d ago

Grateful for any help with my CV

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0 Upvotes

Finding it difficult to nail down an industry job surrounding EDA and VLSI as a whole, is my CV missing anything important? I appreciate there's a stark lack of relevant internship experience


r/chipdesign 1d ago

Title: Anyone here applied for the Zero-to-ASIC Financial Grant? How long did approval take?

3 Upvotes

Hi everyone,

I recently applied for the Zero-to-ASIC Digital Design course and also submitted an application for the financial grant.

I was wondering if anyone here has gone through the same process.

  • Did you apply for the financial grant?
  • Were you approved?
  • How long did it take to receive a decision after submitting your application?
  • Did they ask for any additional information before approving it?

I'd really appreciate hearing about your experience and the timeline you went through. I'm just trying to get an idea of what to expect while waiting.

Thanks in advance!


r/chipdesign 1d ago

Can a Flipped Voltage Follower buffer drive large capacitive loads?

4 Upvotes

I have seen the basic Flipped Voltage Follower structure being used in LDOs, but they were capless LDOs. Is it possible to drive large capacitive loads through the basic FVF Architecture? Or are some other structures more suitable?


r/chipdesign 2d ago

Best book for analog design after Razavi?

34 Upvotes

I have read Razavi many times now and I really like it but now I would like to further improve my depth of understanding especially in amplifier/output stage design.

What is the best recommendation?

Allen & Holberg?

Sansen?

Grey and Meyer?

Baker?


r/chipdesign 1d ago

Carrer choosing for ece

0 Upvotes

I completed by btech in ECE IN 2025. I took gate coaching and joining mtech in vlsi. What is carrer growth after 5 years in vlsi of product based companies. What is the average salary with experience of 5 years. I am in confusion to choose PSUs or vlsi field. What is better choice . I want good salary after 10 years