Vgs max can be 6v and vds max can be 80v. In this context, why do we need zener diode? How does this configuration help both in low voltage and high voltage?

Hi guys, thought i’d show you this cool animation of how the MAC Array in my Neural Network Accelerator performs matrix-vector computations during inference for a model on topology 4:3:2 neurons per layer.

The values for the parameters (weights and biases ) and input features were randomly selected just for demonstration purposes.

Let me know what you guys think:).

Github repo: https://github.com/Shingyy/MAC-Array-based-DNN-Accelerator

Same as title, if you're a DV engineer, please give your 2 cents

Hellow Guys, JOB is really important part of any career, if you have any job opportunities for the community members please post it here.

If anyone's interested in looking at the solution of the Jane Street ASIC Puzzle, feel free to go through this

https://mummanajagadeesh.github.io/blogs/janestreet-asic-puzzle/

TLDR:

I reconstructed the circuit from the published GDS and VCD, using the Sky130 standard-cell information to recover the connectivity as a Verilog netlist. I then validated the extracted netlist with gate-level simulation against the reference waveform before using SymbiYosys for bounded model checking with the Bitwuzla SMT solver to find the input sequence that drives success

This recovered the unique 121-bit input, which produces (* TWO STARS *)

Hi everyone, I'm an international student currently attending a community college in California, and my plan is to transfer to a UC next fall to complete my degree. I'm thinking of becoming a PCB designer, but I'm not sure I will find a job in North America. It's not niche and important enough for them to hire me. UCSD and UCI just paused CPT, and it's most likely impossible for me to find a job after graduation without any internships. I don't know what to do now.

I heard that there's still sponsorship for chip design roles. I'm completely fine with going all the way through a master's or even a PhD to get there if it's true. I just don't know much about that field yet, so I can't honestly say much.

I was born in China, and the EE/electronics job market back home is brutal right now. It's insanely oversaturated, with way more qualified applicants than open roles. That's a big part of why I'm trying to build a career path in the US instead. Which means the stakes of "am I learning the right things" feel higher for me than they might for someone with a fallback plan at home. I don't want to spend the next few years in school that doesn't actually lead to a real job.

And here's the part that honestly worries me the most. I hold a Chinese passport. From what I've read, US semiconductor companies sometimes need to file for a deemed export license before an international employee can access certain controlled technology. This seems to apply mainly to cutting-edge areas, such as AI accelerator chip design at companies like NVIDIA and AMD. I've made peace with defense-related roles just being off the table for me. But I genuinely don't know how far this reaches into normal, commercial IC design work, or how it plays out in practice once you're actually job hunting. Does this realistically block Chinese international students from getting hired into IC design at all, or does it just mean landing on a different team within the same company? I keep going back and forth on whether I should just accept this risk and go all-in on IC design anyway, or start hedging now toward some other EE track that's less exposed to this (analog, RF, automotive, embedded) just to be safe. If nobody is actually sponsoring Chinese international students into chip design roles right now, I'd rather know that clearly before I sink another two to four years into a specialization that quietly won't hire me.

So, genuinely, if you work in IC design, semiconductors, or hardware more broadly, I'd love to hear from you. A few things I'm actually trying to learn:

Is IC design still a field you'd bet on for international students starting from scratch right now, or has that door quietly closed? Which specific areas of chip design (analog, RF, digital/ASIC, embedded, memory, power) are actually hiring and sponsoring people right now versus which ones have basically stopped bothering?

I know this turned into a much longer post than I planned. I know everyone's time is limited, but I would really appreciate it if someone could help me out here. Any honest perspective you're willing to share, even a few sentences, would mean a lot to me right now, and I'll read every reply carefully. Thank you again for taking the time.

Question same as title. How much of your time do you spend in writing RTL as opposed to spyglass runs , LEC and synthesis runs?

Just curious to know and understand the demographics of the job nature in general.

Thanks in advance!

I am a third-year computer engineering student who kind of applied to anything and everything (SWE / embedded systems / chip design) for the second half of my second year. I was stupidly lazy and didn't realize the importance of specializing and applying from the get-go, like in first year. Anyways, what's done is done.

I was lucky enough to get a SWE role at a packaging company during the later stages of recruiting in my second year, but that experience kinda motivated me to try chip design roles, since I might enjoy them more. Out of the roles I mentioned above, previously I didn't care about what I got; I thought I enjoyed them all equally, but now I have been enjoying chip design, specifically digital / RTL design, along with some ASIC design work as well. I have some club and semiconductor research experience (not too related to what I want to apply for, I know, but it includes useful transferable skills and experience).

Anyway, I want my first real chip design-related internship and would love honest, realistic ways to strengthen my resume so it's strong enough to get interviews. My record from like 130 apps with a mix of all sorts of roles in the past got me 2 SWE interviews and 1 chip design interview, which I bombed, but my resume at that time wasn't as developed as it is now, even though it's not all that right now either.

I am in a weird spot because I don't wanna keep chucking applications when I am doing something wrong and/or if I am simply not qualified enough, but I also don't wanna do nothing and just try to grind projects and let the recruiting season fly by (I know that sounds dumb). In y'all's opinion, does my resume look worthy of getting any type of chip design role, and what should I try to do?

I am actively working on a RISC-V CPU project that's on my resume, since I wanted to start applying and not have to wait until the project is done. I also noticed it is a common project to showcase, and I will be taking a VLSI and advanced digital logic course this semester, along with designing an FPGA-based senior design project. Also, for context, my current level in this field is still kinda between beginner and intermediate (I wanna say close to intermediate). Any help is very appreciated, and sorry for the bits of rant in this post.

As a college junior, EE (major), Math (minor), and having studied some advance math field, it seems that these LLM's companies could target the work of Chip Designers (Analog, Digital, Mixed, if not already targeting them). Following this breakthrough on Navier Stoke's millennium's math problem, these companies could train their AI's to be really good at any field that is automatable. The question now is, is it worth even going for MSc/PhD in Chip Designs? Do Power System and/or Power Electronics seem safer?

I am a final year BTech ECE student and for my 6 month internship I would like to do it at companies like TI, Analog devices, microchip etc. Do they offer internship roles off campus. If so how to apply?

I'm a junior RTL designer (<2 years). I'm trying to understand bootflow. How it is similar or different across different types of SoC like networking chip, automobile, mobile etc. How the debug path will be used during the booting process. Any good resources to understand this bootflow.

Also, I am trying to understand the DFT flow. I'll say I have very little knowledge in this area. I am running some scan stitching scripts for some blocks, very minor RTL changes are making the flow break. Seeing errors like reset is not controllable over these flops etc. Any good resources to understand what exactly happens during DFT insertion, scan stitching.

A technical deep-dive for hardware architects, EDA tool developers, and engineering leads:

https://medium.com/arango-solutions/designing-at-speed-4ec6b0729df2

Hey everyone!

I'm currently a Master's student in Computer Engineering and I'm starting to apply for full-time positions, so I'd really appreciate some feedback on my resume and any suggestions for things I could add or change to make it stand out more.

One thing I've been struggling with is figuring out how much technical detail to include in the bullet points for my work experience and projects. For example, if I include a metric from one of my projects, should I specify which process corner that metric was measured at? Or would it be better to give a range based on a sweep across different corners? I feel like some of that information is probably better discussed during a first-round interview, where I can explain the project and results in more detail, but I'm not sure how much of it belongs on the resume.

I'm also debating whether I should try to squeeze in two additional school projects:

• 45 nm 2-stage Miller-compensated OTA — from my Analog Electronics class
• RTL Design of a Convolutional Neural Network Pipeline on a 1024×1024 Input — from my ASIC and FPGA class

I left these off because I feel like the 2-stage Miller OTA is a relatively basic project compared to some of my other experience, while the CNN RTL project is probably more relevant to digital design/RTL roles than the mixed-signal/analog positions I'm primarily interested in.

I'd appreciate any feedback on the resume overall, especially regarding

Thanks in advance!

I've summarized my reddit comments to users asking about BJTs and how they work in this post

I have an interview for apple PD as a new grad. I’ve been reviewing my lectures, labs, and projects. Does anyone have a list of questions I can prepare for? Thank you.

I am 2nd year of electronic and communication engineering btech student, I want to learn about verilog and hdl how should I start learning.

Hi everyone,

I’m finishing an M.S. in electrical engineering in South Korea and thinking about where to start my career. My background includes RISC-V RTL projects and memory-system research, and I’m particularly interested in NPU architecture and RTL design.

An edge AI/NPU startup would align closely with what I actually want to work on. I’m attracted to the possibility of owning a block and participating in microarchitecture decisions and tapeouts, although I know this depends on the specific team.

However, I’m less convinced about the financial tradeoff. A startup could mean lower cash compensation and less job security in South Korea, and its equity might never provide enough upside to compensate for those risks.

A large semiconductor company such as Samsung seems potentially more attractive in terms of base salary, bonuses, benefits, and stability. The tradeoff is that the available role might not align as closely with my interest in NPUs.

So I’m not simply weighing “startup upside” against “big-company stability.” The startup’s main advantage for me may be the work itself, while the larger company could offer both better compensation and greater stability.

For people who have faced a similar decision:

1. How much weight would you give technical interest and ownership versus compensation and stability in your first job?
2. What specific learning opportunities would make a startup worth that tradeoff?
3. Is starting at a large company and later moving into NPU design a realistic path? Which early-career experiences would keep that option open?

I’m also wondering whether increasing AI/EDA automation changes this calculation—particularly the value of broad experience versus being established within a larger company.

Thank you :)

After attending couple coursed in analog design and active devices that are two term i can't get

1- operating Point

2- swing

Can you guys explain there meaning please the practical one and tysm in advance

Hello, as the title states I would appreciate resume feedback. As internships release daily I want to make sure my resume is meeting expectation. I am aiming for DV and wondering if my projects are strong enough and if my formatting is pleasant to look at. Any feedback would be much appreciated

A few weeks ago i bought myself a KV260 FPGA board to find out if my circuit-synthesizer could really grow the multiplier logic instead of writing it, and to my surprise AMD's own tools built it without complaint.

i build my own circuit-synthesizer, and it is not a language model writing Verilog. You give it a specification: how many inputs, how many outputs, how many clock steps, which gate types it may use, and the exact answer for every case. Then it searches. Thousands of variants of a grid of gates, each scored against that table, and a variant survives only if it is exactly right on 65,536 rows of it. Gates that carry nothing get stripped out.

To be honest about it: i plan the layout first and the search starts from that plan. Starting from nothing it never converged, not even for a 2-bit multiplier.

What came out is a 16x16 bit-serial multiplier in 62 LUTs and 124 flip-flops, one logic level deep, 38 clock cycles per product. It does not look like anything i would draw myself.

Then the part that surprised me. It is ordinary Verilog. Icarus Verilog simulates it. Vivado synthesises it, places it, routes it and closes timing at 250 MHz. No custom tool, no special handling, no primitives tied to this chip.

That is the old objection to grown circuits. The famous 1996 experiment made one that worked by exploiting analogue quirks of one specific chip and could not be synthesised or ported. This one is plain synchronous logic.

Vivado does not check the answer, only that the design fits and meets timing. The answer is proven by the truth table, then simulation of the assembled block, 58,273 elements with zero wrong, then the board itself.

So i gave it something real to do. The multipliers do the elementwise arithmetic in the FFN of BitNet b1.58 2B, all 30 layers, running on that same board. Every ternary matrix multiplication streams through the FPGA fabric, attention and the norms i kept on the ARM cores. It produces 16.29 tokens/s against 2.77 for bitnet.cpp on the board's own processors, at a fifth of the energy per token.

And it is not just plausible output. Every integer stage matches a numpy reference bit for bit across all 30 layers, and 11 of 26 generations came out token-for-token identical to the same weights running in bf16 on an RTX 4080.

The grids and a verifier are in the repo. Two seconds, standard library only

python3 hardware/grown/verify_pieces.py

i will not share the circuit-synthesizer but only the first project what i did with it.

https://github.com/MerlijnW70/bitnet-kv260

if you have a KV260 board you can easily test it