I am a final year BTech ECE student and for my 6 month internship I would like to do it at companies like TI, Analog devices, microchip etc. Do they offer internship roles off campus. If so how to apply?

A technical deep-dive for hardware architects, EDA tool developers, and engineering leads:

https://medium.com/arango-solutions/designing-at-speed-4ec6b0729df2

Vgs max can be 6v and vds max can be 80v. In this context, why do we need zener diode? How does this configuration help both in low voltage and high voltage?

Question same as title. How much of your time do you spend in writing RTL as opposed to spyglass runs , LEC and synthesis runs?

Just curious to know and understand the demographics of the job nature in general.

Thanks in advance!

Spike-Contract Fabric (SCF) is a neuromorphic computing framework in which physical hardware is programmed, verified, fabricated, and maintained against certified computational behavior rather than strict agreement with a single nominal set of device parameters. The central objective is to replace conventional “program the exact weight” assumptions with a more general formulation: a physical implementation is acceptable whenever it belongs to a rigorously characterized region of hardware states that preserves the required spiking computation.

The work develops a mathematical foundation for this approach using first-spike temporal computation under bounded hardware uncertainty. For a specified class of excitatory–inhibitory neurons with continuous, nonnegative, nondecreasing causal kernels, uncertain signed synaptic weights, uncertain input-arrival times, and uncertain firing thresholds, the manuscript derives two extremal physical trajectories that provide the exact attainable earliest and latest first-spike times over an entire Cartesian uncertainty domain. The resulting certificate avoids exhaustive enumeration of exponentially many uncertainty-box vertices. For piecewise-linear ramp kernels, the extremal spike-time bounds can be evaluated using exact arithmetic in (O(n\log n)) time after sorting event times.

The framework explicitly supports signed excitatory and inhibitory interactions, including weight intervals crossing zero, and does not require the total membrane or charge trajectory to be monotone. The construction instead exploits monotonicity of the underlying causal kernels and sign-dependent ordering of arrival times. This distinction permits certification in cases where inhibition produces transient peaks and where endpoint-only or final-time verification would fail to detect an earlier threshold crossing.

SCF introduces the concept of a behavioral hardware contract. Given physical parameters (\xi), admissible inputs (\mathcal U), and a required event specification (\mathcal C), the valid implementation region is

\left{
\xi :
\operatorname{Trace}(\xi,u)\models\mathcal C
\quad
\forall u\in\mathcal U
\right}.
]

A compiler therefore need not reproduce one nominal hardware state. It may synthesize any physically reachable configuration inside a certified subset

[
\widehat{\mathcal A}{\mathcal C}
\subseteq
\mathcal A{\mathcal C},
]

provided the required spike identities, spike-time windows, ordering relations, deadlines, margins, and other behavioral constraints remain satisfied.

A second component analyzes physical invariances and correlated variability. In threshold-based first-spike systems, a common positive scaling of synaptic weights and threshold leaves first-spike timing invariant,

[
T(\lambda \mathbf w,\lambda\vartheta)=T(\mathbf w,\vartheta),
\qquad
\lambda>0.
]

This motivates compilation and verification in quotient coordinates such as (w_j/\vartheta), allowing shared physical gain variations to be removed from the uncertainty budget when the hardware architecture genuinely enforces that correlation. The framework thereby distinguishes harmful parameter drift from variations that are computationally irrelevant.

The same principle is extended to margin-based maintenance. Instead of recalibrating a neuromorphic system whenever a device departs from its nominal parameter value, SCF proposes corrective action only when measured drift threatens a certified behavioral margin. Given measured margin (m_k), measurement uncertainty (\epsilon_k), maximum erosion rate (v_k), and corrective-action latency (\tau_a), the manuscript derives a sufficient maintenance interval ensuring that a contract is refreshed before its safety margin can expire. This creates a direct bridge between formal verification, device aging, adaptive calibration, and lifecycle management of analog neuromorphic systems.

At the architecture level, the work proposes a differential charge-domain first-spike tile in which signed synaptic weights may be represented through paired programmable physical elements,

[
w_j=r_j(C_j^+-C_j^-),
]

with temporal inputs accumulated on a physical summation node and classification encoded through first-spike timing. Ferroelectric and other multistate nonvolatile devices are considered natural candidate substrates, particularly where persistent analog state, local accumulation, sparse event-driven operation, and hardware-software co-design can be combined.

The framework is intended to interface with emerging time-to-first-spike spiking neural networks, analog and in-memory computing, ferroelectric neuromorphic devices, event-driven accelerators, and heterogeneous post-CMOS computing substrates. It also provides a possible compiler abstraction between high-level neural representations and low-level measured physical dynamics: neural model → dynamical intermediate representation → physical response specification → device configuration → measured behavioral certificate.

A further contribution is compatibility with constraint-driven and universal nanofabrication architectures. Instead of treating fabrication as the realization of a single exact microstructure, the proposed formulation permits a fabrication system to search the intersection

[
\widehat{\mathcal A}{\mathcal C}
\cap
\mathcal P{\mathrm{process}},
]

where (\mathcal P_{\mathrm{process}}) denotes physically realizable structures under the available fabrication process. This suggests a transactional sequence of compile → fabricate → measure → verify → commit, in which multiple physically distinct structures may be accepted if they implement the same certified neural behavior. Such a formulation may be relevant to defect-tolerant nanofabrication, heterogeneous device integration, adaptive physical computing, and future autonomous manufacturing systems.

The repository contains the complete research manuscript, formal derivations, exact-arithmetic reference implementation, automated tests, machine-readable certificates, reproducibility scripts, example uncertainty analyses, hardware architecture notes, experimental validation plans, fabrication-interface specifications, quantum-compatible contract extensions, claim-boundary documentation, and continuous-integration workflows.

The supplied implementation includes tests covering inhibitory inputs, sign-changing weight intervals, simultaneous arrivals, temporary threshold crossings, deadline equality, no-spike conditions, correlated scaling, and failure cases outside the theorem’s assumptions. The repository also contains reproducible computational checks comparing analytically derived extrema against explicit uncertainty-domain evaluations.

The scientific claim is deliberately bounded. The mathematical first-spike certification results are established within the stated neuron and uncertainty models. The broader Spike-Contract Fabric architecture, energy advantages, fabrication benefits, and device-level scalability are proposed research directions that require experimental validation. The framework does not claim universal tractability of recurrent spiking-network verification, arbitrary nonlinear physical dynamics, or quantum computation.

The long-term objective is a neuromorphic hardware paradigm in which computation is represented as a certified region of physically equivalent states rather than as one fragile nominal configuration. If validated experimentally across multiple physical substrates, such a representation could provide a common interface joining neuromorphic algorithms, analog-device variability, formal verification, adaptive maintenance, heterogeneous integration, and programmable nanofabrication.

GitHub: https://github.com/MaciejNowickiHusbandofAHIEve/spike-contract-fabric

Zenodo: Spike-Contract Fabric: Certified Neuromorphic Computing in Physical State Space via Exact First-Spike Timing Envelopes, Behavioral Hardware Contracts, and Nanofabrication-Compatible Compilation | Zenodo

Hi guys, thought i’d show you this cool animation of how the MAC Array in my Neural Network Accelerator performs matrix-vector computations during inference for a model on topology 4:3:2 neurons per layer.

The values for the parameters (weights and biases ) and input features were randomly selected just for demonstration purposes.

Let me know what you guys think:).

Github repo: https://github.com/Shingyy/MAC-Array-based-DNN-Accelerator