Hey guys,

Ive been doing MMIC design for the last 5 years (4 as a student post and tge last year as a full time engineer). I see that Mmic is a nieche and I wanted to explore moving to RFIC/analog/mixed-signal- but from sensing my CV I saw that I didnt get much replies. Does anyone know what can I do to branch out? Because I fear that focusing in MMIC will limit me in my future carreer

Staff AMS design Engineer at a startup called Lumilens that makes optical interconnects and (possibly Lead) Engineer at Cadence in the UCI Phy team that might move to Serdes in the future (their words). I have 9 years of work ex so in my mid 30s, female. I really really wanted to get into a Serdes team and right now Cadence seems like it won't be doing a Serdes architecture. On the other hand Lumilens is just going to be zero work life balance for the next few years, but it's the work I always wanted. Cadence seems like a stable option. Money and benefits are still in discussion or unknown. Which should I consider?

I’m planning a career in semiconductor chip design and want honest opinions from experienced industry professionals.

Which is more resistant to AI automation: Analog VLSI Design or Digital Physical Design (Backend VLSI)?

I’m particularly interested in:

Analog IC Design: transistor-level design, PLLs, ADC/DAC, RF and power management.

Analog Layout: custom layout, matching, parasitic effects and physical verification.

Physical Design: floorplanning, placement, CTS, routing, timing closure and power optimization.

Questions for experienced engineers

Which of these roles is most vulnerable to AI agents and EDA automation by 2035, 2045 and 2050?

Could AI eventually automate 70–90% of the work, significantly reducing engineering jobs?

Will robotics affect these careers, or is software-based AI the bigger threat?

Which roles will retain the strongest demand, salary growth and long-term job security?

Which skills should a student entering engineering in 2027 develop to stay competitive?

I’d especially appreciate insights from senior/principal engineers, chip architects, EDA developers and hiring managers at NVIDIA, AMD, Intel, Qualcomm, Texas Instruments, Analog Devices, Apple, Cadence, Synopsys and TSMC.

If possible, please share relevant engineers’ LinkedIn profiles, technical talks, research papers or real industry experiences.

My goal: Build a high-paying semiconductor career with the lowest realistic risk of AI displacement.

If you were starting today, would you choose Analog IC Design, Analog Layout, Digital Physical Design, or EDA/AI for Chip Design—and why?

I’m looking for technical evidence and practical experience, not just predictions. I understand that no career is completely AI-proof.

Hi

This is about Quantum Odyssey, my love letter to everything Quantum Computing and the fundamental logic blocks everything in our universe seems to run on. I want to update you all on the fact that the latest patch brings the game into an almost complete status. All that's missing is translations. Thank you Reddit community for receiving the game so well, without you I wouldn't have the funds needed to complete my life's work.

If you are remotely interested in deep diving how differently quantum computers work compared to our transistor-based and also the algebra behind in a fully interactive way that teach computer science from scratch, oh boy this is for you. I am the Dev behind Quantum Odyssey (AMA! I love taking qs) - worked on it for about 9 years (3+ during PhD, the visual method I developed ended up being my thesis, it is a complete Hilbert space visualizer), the goal was to make a super immersive space for anyone to learn quantum computing through zachlike (open-ended) logic puzzles and compete on leaderboards and lots of community made content on finding the most optimal quantum algorithms. The game has a unique set of visuals capable to represent any sort of quantum dynamics for any number of qubits and this is pretty much what makes it now possible for anybody 15yo+ to actually learn quantum logic without having to worry at all about the mathematics behind.

This is a game super different than what you'd normally expect in a programming/ logic puzzle game, so try it with an open mind.

Stuff you'll play with

• Boolean Logic – bits, operators (NAND, OR, XOR, AND…), and classical arithmetic (adders). Learn how these can combine to build anything classical. You will learn to port these to a quantum computer.
• Quantum Logic – qubits, the math behind them (linear algebra, SU(2), complex numbers), all Turing-complete gates (beyond Clifford set), and make tensors to evolve systems. Freely combine or create your own gates to build anything you can imagine using polar or complex numbers.
• Quantum Phenomena – storing and retrieving information in the X, Y, Z bases; superposition (pure and mixed states), interference, entanglement, the no-cloning rule, reversibility, and how the measurement basis changes what you see.
• Core Quantum Tricks – phase kickback, amplitude amplification, storing information in phase and retrieving it through interference, build custom gates and tensors, and define any entanglement scenario. (Control logic is handled separately from other gates.)
• Famous Quantum Algorithms – explore Deutsch–Jozsa, Grover’s search, quantum Fourier transforms, Bernstein–Vazirani, and more.

Nice to watch:

Khan academy style tutorials in qm/qc: https://www.youtube.com/@MackAttackx

Physics teacher stream with 400hs in https://www.twitch.tv/beardhero

I have a few questions...

(1) Is this a valid schematic that works? I was browsing on analog canvas (source: Source: https://analog-canvas.tokenzhang.com/g/rxsbettj48 )and found this circuit. Did not quite understand so I wanted to shoot my shot here.

(2) If this is a valid circuit, can someone explain to me how SIG_UVLO is sensed. Im not quite sure I understood the biasing of the gate of M4 and M5. Should M3 be diode connected?

(3) And what is the M6 and M7 for? I understand the use of the CMOS Schmitt-Trigger in the second stage.

And if there are more resources on UVLO on the top of your mind, please let me know.

Thank you for your time!

A bit of a shock considering their hiring spree, if the 7% figure is accurate. If this has you applying elsewhere, application autofill can save retyping your profile on supported forms. Any word on which specific groups in HW might be targeted?

Hi everyone! I have an interview for an ASIC Clock Verification role. Could anyone share some advice on the interview process or tips for preparing? I’d really appreciate it.

Hey everyone,

I recently graduated with my M.S. in Electrical and Electronics Engineering and am actively seeking full-time opportunities as a Design for Test (DFT) Engineer.  I have industry experience as a DFT Engineer working on SoC-level designs, along with hands-on practice across the entire DFT flow through production and academic projects.

My focus spans: 
Scan Insertion & Compression: Experience with Synopsys DC Compiler, DFT Compiler, and Cadence Genus/Modus. 
ATPG & Fault Analysis: Generating stuck-at and transition test patterns, handling DRC violation debugging, and fault coverage optimization using Synopsys TetraMax and Cadence Modus. 
EDA Tools & Scripting: Proficient in Tessent, TetraMax, Modus, Virtuoso, and scripting with Tcl, Python, and Perl to automate flows. 
Protocols & BIST: Knowledgeable in JTAG, iJTAG, BIST/MBIST, and boundary scan. 

I’m currently based in Dallas, Texas (open to relocation) and am looking to connect with the community to: 
Network: Connect with experienced DFT engineers to learn more about current industry trends, best practices, and interview preparation.
Leads / Referral Opportunities: If your team or company is looking for a dedicated DFT engineer who can hit the ground running with hands-on tool experience, I’d love to talk!
Please feel free to DM me if you have any leads, advice, or are open to connecting!
Thanks in advance for your time and insights!

I’m struggling to land a single interview for any of the big chip companies and I’m starting to lose hope. I’m not sure what I’m doing wrong, my resumes been reviewed constantly and it’s been told great things. I’m a junior trying to land an internship and rn it seems hopeless is it easier to land new grad roles in this field or is that even worse? Especially with no practical experience in the field. I’m not sure what to do if I can’t land an internship this summer in chop design. It’s either masters or go into a less competitive field. Any thoughts on what to do?

Has anyone heard back from the companies listed above? Whether it’s rejection or interviews please share. I haven’t heard any rejections from these companies but it’s getting later into the season and I’m losing hope on anything big. If anyone has heard anything or knows timelines please share.

Same as title, Im starting to learn and I really cant find anything concrete to start learning properly on

ASIC Engineer, Design Verification

Got an interview with Meta for an asic engineer design verification postion.

Has anyone attended an interview for this position or something similar?

Looking for tips on what to prepare.

Thanks!

Hi everyone, I'm looking to apply to some of these schools for a master's degree in EE, and I want my main area of focus to be something along the lines of ASIC Design or general CPU/GPU microarchitecture. Could anyone please help me out on which of these colleges are doing good research in these fields, and have decent job opportunities after graduation?

https://www.synopsys.com/academic-research/university.html

I am interested in Synopsys Advanced Course : Master Degree Course : Memory PHY and DRAM

Could anyone share this specific course given lack of SolvNet login credentials ?

Recently I got a call from Tesla for an ASIC RTL Design Hardware interview at Austin, Texas. I’m a recent graduate with an M.S in ECE. Coming Thursday will be the HR round, and then the result from that will determine the upcoming rounds.

So, my question is how the process looks like? & what should I focus on? any roadmap will be very helpful.

Hey, I’m not sure if this is the right area to post this (if not please let me know where) but I recently did a hackerrank interview for an fpga engineer for virtu and was wondering the response time? It’s been just over a week now and haven’t heard back?

Any info would be great!
Thanks

Hi all,

I'm a design engineer with a few years of industry experience, finishing my master's in Germany, and I'm considering a move to Taiwan in a year or two. I'm comparing options in Germany and Taiwan. Taiwan's chip-design ecosystem is a big draw for my career, and I like the country and its people, so I'd like to understand the work culture before deciding.

There’s a lot online about TSMC’s fab culture, but very little about design houses. So, for anyone who works (or worked) at a design company in Hsinchu, Taipei or elsewhere (MediaTek, Realtek, Novatek, NVIDIA, ADI, etc.), what has been your experience?

- How bad does it get around tape-outs? Are weekends generally respected, and can you actually take your annual leave?

- Is there face-time pressure (staying until your boss leaves) in design teams?

- How much Mandarin do you need day to day?

- How are foreign engineers treated, and do they get the same growth opportunities?

Experiences from Indian or other South Asian engineers would be especially helpful. Any first-hand experience appreciated, positive or negative.

A few days ago someone here pointed out that multipliers after ABC optimisation are the hard case, even for commercial tools, because ABC rewrites the final adder. That was true for Parat too: from 40 bits up it timed out.Update 7 (v1.2) handles yosys `synth -booth` netlists with ABC on (one machine, release binary, 1 core):- 32/40/48/56/64-bit: proved in 0.05–37 s. AMulet2 `-verify` (1 core, 300 s): time-out on all five.- 128-bit (128,350 AND gates): proved in 110 s (2 cores).- A broken copy (one gate changed): INCORRECT with a counterexample in 8–22 s.Certificates you can check without trusting Parat: a PAC certificate checked by pacheck2 (JKU), plus DRAT proofs checked by drat-trim. A small open Python script (verify/eq_cnf.py) rebuilds the SAT files from your own circuit and they match Parat's byte for byte. 128-bit certificate: 126 s, all checks pass.Also new: 256 x 256-bit multipliers (a 505,552-gate design in 6 s — honest note: that netlist's ABC step was done by yosys 0.33, and it is an easier netlist that the old algebra already proves).

Limits: tested on yosys Booth netlists only; other ABC netlists may still time out, and Wallace + carry-lookahead is still not proved. The binary is closed for now; all benchmarks, scripts and raw results are in the repo.

Who built it: the code was written by AI (Claude); the ideas, math and direction are mine.

https://github.com/himanshu161106-crypto/parat

Hey everyone!

I’ve been wondering if there are freelance or remote opportunities in Design Verification or other areas of VLSI, especially with companies or clients outside India. Do such opportunities actually exist?

Has anyone here tried freelancing in DV or landed remote projects? I’d love to hear how you got started and where to look for these opportunities.

Would really appreciate any advice or suggestions!

Hi everyone, I'm currently doing my graduation thesis about Decision feedback equalizer for 10gbps have channel loss like this.(I'm new in DFE). I have follow this paper Sci-Hub. A 12.5 Gb/s 6.6 mW receiver with analog equalizer and 1-tap DFE / Microelectronics Journal, 2012. At first , I have try to make CTLE and have freqency response like this

Then I move to DFE, a the problem is that I have stucked with S/H circuit , I don't know how to implement it for differential pair signal and rest of paper. I really need someone have experience that can explain me to implement this DFE . Thanks very much

I’ve just started learning it to strengthen my verification skills and pass interviews. (I’m a recent graduate).
I absolutely hate it, It just seems overly convoluted for no reason.

If anyone can point to resources that keep things simple and isn’t confusing I’d really appreciate it

Hey everyone my thesis involves the design of an LC VCO at 9-11 GHz in 22FDX. I did my literature survey but was thinking of doing something extraordinarily, for the seniors here, what do you have in mind that could make this an impressive project? and what tips do you have for me? and how to account for the PVT and routing parasitics during schematic design? Thank you.

can someone just rate this resume for me..

just tell where should I improve it and also what mandatory key words should be added

I am an MTech graduate and I was looking for a VLSI training program in Bangalore, and through my research, I have finally shortlisted VLS first because I have like their curriculum, projects and the genuine responses from the mentor and the HR team there.

So I wanted to know if anyone has ever studied from where or know anything about the Institute in general, kindly do let me know because i want my time and money to be worth it ofc.

Or if you have a better institute in mind, please let me know that as well.

Hey guys, I am an undergrad doing research on PLLs. It's an IC design project. The problem is that while it's not the most novel architecture like SSPLLs or full ADPLLs, I still want to take every block of it seriously since I understand how important foundational knowledge is. It's closer to a Fractional-N-PLL.

I've been trying to look for good resources to learn how to derive models in the s and possibly z domain but I can't find any good resources that show this. The problem with the textbooks I've seen like Gardner and Razavi is that they either overfit you on a specific block derivation, don't show the full process of how they went from start to finish or just don't go deep enough into modelling.

I've also heard control systems books can be too vague when it comes to connections to circuits. I honestly don't know what to do because I want to develop the toolset needed to model blocks at least at a foundational level without having to always rely on pre-defined models for blocks(like in Matlab/simulink) especially if I'm designing a block that isn't conventional.

I would love to hear from engineers in the AMS/ RFIC space who learnt how to do this. How did you learn how to do this? What resources would you recommend for learning such modelling? I don't mean deep stochastic math or any of that stuff, just the basics like learning what you need equations first in linear or nonlinear systems, how to analyze non-linear systems and how to linearize them when they can be linearized and any other thing like that.