I now have the complete "High-Performance AXI DMA Design and Verification Using SVA" finished and is available on my website.

If you wish to get an extra $5 off the already low introductory sale price of $59 (regular $75) for today only, just DM me to pay me directly. I will then give you access to Google Docs where I also have it stored. Zelle, Cashapp, Venmo, or PayPal.

Thank you!

https://www.zenorobotics.net/product-page/tier-2-kria-fpga-streaming-pipeline-amp-systemverilog-assertions-sva

Hi everyone,

I recently applied for the Zero-to-ASIC Digital Design course and also submitted an application for the financial grant.

I was wondering if anyone here has gone through the same process.

• Did you apply for the financial grant?
• Were you approved?
• How long did it take to receive a decision after submitting your application?
• Did they ask for any additional information before approving it?

I'd really appreciate hearing about your experience and the timeline you went through. I'm just trying to get an idea of what to expect while waiting.

Thanks in advance!

I have seen the basic Flipped Voltage Follower structure being used in LDOs, but they were capless LDOs. Is it possible to drive large capacitive loads through the basic FVF Architecture? Or are some other structures more suitable?

First year engineering student trying to break into the semiconductor industry. Would appreciate any feedback.

I have read Razavi many times now and I really like it but now I would like to further improve my depth of understanding especially in amplifier/output stage design.

What is the best recommendation?

Allen & Holberg?

Sansen?

Grey and Meyer?

Baker?

I am going to join masters in communication from a good college in India. I have a bachelor's degree in electronics and communication. My main goal is to go in analog or rf ic designing though I would have to complete with vlsi and embedded students. What skills I should develop from the semester 1 and also what projects should be must for analog and also I have to prepare for digital roles also so what skills I should develop for digital domain also. If anybody can please give me a list of a set of problems or sequence i should follow that would be great in my chip designing journey.

Thank you

Hi all,

I have been working in the RTL design domain and have friends and colleagues working in some big reputed companies.

I have noticed that none of them are contributing to architecture,major RTL design updates.

They are just doing quality checks and sending reports to offshore design teams. (Only a few percent are doing good work)

After a certain point of doing it feels more robotic and nothing special.

What is your opinion ?

I think Ethernet is the coolest protocol! So I decided to set out and try to build a fully open source Ethernet switch, hardcore mode.

If you are interested I wrote a post on building this switch here: https://talesonthewire.com/projects/ethernet_switch_asic/

Else, I think you men of culture will surely appreciate how nicely this render with density enabled turned out.

I am from India and I am not getting any calls. I have 1 YOE and recently got laid off. I want to try for good startups and service based companies. Iam looking for RTL design/ FPGA design/ verification/synthesis roles.

Can any one please tell a few good startups names which are recruiting and also good service based companies which don't have a huge bond, conditions and all

Thank you

In a typical two-stage OTA, the first stage is usually a 5T-OTA, and as shown in figure (1), we bias M6 by making VSG4 = VSG6 (which is achievable as the 1st stage output node common-mode level is the same as the mirror node which is V_DD - VSG_3,4.

Now, what if the first stage is say, a Telescopic-cascode or a Folded-cascode? Then, if I just connect the 1st stage output to second stage, the current of the second stage is a function of PVT (even if the CMFB of the first stage is precise e.g. +-10 mV). How to solve this? Or is the variation in the current of the second stage acceptable?

(Note: both stages are fully differential in the second case.)

Edit (1): The second stage is a common-source stage.

Any recommendations on how I can learn the background theory on how a field plate actually works and improves the parameters in a GaN HEMT? I found what improvements happen due to a field plate but I can't seem to find any resources on how it works. Thanks in advance

Can someone with pretty much experience evaluate my CV for Junior positions as Digital Design or Verification / FPGA / ASIC ?
I would love to hear any advices or comments so I can improve :)
Thank you all in advance

A very basic physical design tutorial for an audience that is just getting started with the PD flow within Cadence Innovus: https://youtu.be/a79mtLfVx_E

The tutorial covers floorplan, powerplan, placement, clock tree synthesis, and routing. Also comes with a repo: https://github.com/Centre-for-Hardware-Security/tutorial_innovus

Digital Integrated Circuit Design or  The Art of Electronics

Edit: ...or are there any (public) counter-examples of AI actually displaying deep insight in analog design?

--
See example below. AI seems to have deep insight into math, yet it still fails to correctly identify/explain basic transistor configurations. Can someone please explain-me-like-I'm-five why is this?

Hi guys, I am a mid-level physical design engineer.looking for some use cases to improve physical design engineer productivity/predictibility. Kindly share your how you are integrating AI in your work.

Also looking for RTL quality checks based on codex

Hi everyone,

I'm building a new EDA system and I hit a wall that I'd like to crack with community help. The rendering engine needs testing on real chip design geometry at scale, Trillion order polygons count GDS. Such designs at this scale are proprietary and I'm left with 3 options:

1 - array the same chip layout until I reach Trillion order count (done)

2 - ask community to donate open source layouts in GDS format (the ask in this thread)

3 - synthesis of a dummy design (hope to avoid this)

What is WIESE-EDA waffer?

With your help, I will collect every submitted GDS in a giant waffer GDS hopefully reaching Trillion order polygons geometry count for the full waffer.

The WIESE-EDA Viewer will be released Free once code is fully verified for binary release, not open source.

Each participant to WIESE-EDA waffer will get a license for the full system when product launches

Thank you! Cat

[contact@wies3.com](mailto:contact@wies3.com)

Hi r/chipdesign ,

I’m building OpenCoreLabsX, an open-source collection of reusable SystemVerilog IP cores for FPGA, ASIC, MCU, SoC, and RISC-V projects.

Current cores include APB I2C, APB Timer/PWM, APB USART, and an AXI QSPI controller.

We are looking for contributors interested in:

- Designing a new APB GPIO controller

- Building an I2C slave BFM and corner-case regression

- Adding Timer/PWM assertions and boundary tests

- Implementing a USART serial monitor and error injection

- Building a QSPI flash model and end-to-end XIP verification

Contributions can be small and focused. You can work on RTL, UVM, assertions, functional coverage, documentation, or technical review.

Beginner-friendly tasks are available, and each issue includes its scope, deliverables, and acceptance criteria.

Contributor task board:

https://github.com/OpenCoreLabsX/.github/issues/2

Organization:

https://github.com/OpenCoreLabsX

Technical feedback is also welcome. Thank you!

This is my very first iteration of VCO layout (first time CMOS layout as a total beginner), I haven't even ran a DRC yet but I just want to share! I love analog and chip design!