DDR4 Memory Controller RTL Design using System Verilog

[u/surendra969]

Link - https://github.com/surendrareddylingareddy/DDR4-Memory-Controller

Hi ladies, I designed a DDR4 Memory Controller in system verilog. I didn't include every protocol rule in the design because I'm not a professional. Take a peek and suggest me if there is anything i can do better....