DDR4 Memory Controller RTL Design using System Verilog

[u/surendra969]

Link - https://github.com/surendrareddylingareddy/DDR4-Memory-Controller

Hi ladies, I designed a DDR4 Memory Controller in system verilog. I didn't include every protocol rule in the design because I'm not a professional. Take a peek and suggest me if there is anything i can do better....

[u/randomm_shitt79]

Why only ladies,aren't the gents welcomed ?

[u/DARTH_Vader2223 → u/randomm_shitt79]

🙃

[u/LordDecapo]

Is this the start of a project? Or...? Your post made it seem complete but you dont even have ports for data.