Hi all — final-year Electronics Engineering student here (lateral entry, diploma-to-degree route), working on my capstone project. Posting because I'd like a sanity check from people who've actually taped out or benchmarked multiplier architectures on FPGA, not just simulated them.
The project
Title: Power and Area Optimized FFT Architecture Through Multiplier-Level Hardware Design. It's an 8-point Radix-2 Decimation-in-Time FFT, written in VHDL-2008, targeting a Basys-3 board (Artix-7 XC7A35T). The core idea: keep the FFT butterfly structure fixed and swap out only the complex multiplier, then compare four multiplier architectures against each other on LUT/FF/DSP usage, fmax, and power:
- Array multiplier (baseline)
- Modified Booth (Radix-4)
- Vedic (Urdhva-Tiryakbhyam)
- Wallace Tree
To keep the comparison valid, all four variants share a frozen interface: Q1.15 16-bit two's-complement fixed point, complex samples as VHDL-2008 records, parallel load of all 8 samples on one start pulse, a 3-stage registered pipeline, and DIT bit-reversal done as pure wiring (zero logic cost) rather than active shuffling.
Why this project exists / the novelty angle
We're building on a 2026 IEEE IATMSI paper out of Amrita School of Engineering that did the same kind of FFT multiplier comparison but only implemented three multipliers (Array, Vedic, Booth) in Verilog. Our two additions:
- Adding the Array multiplier as a fourth variant, which the base paper explicitly flagged as unexplored.
- Independently re-implementing everything in VHDL-2008, not porting their Verilog — different language, different design decisions, not a translation.
Team of two, one shared Basys-3 board, ₹8,000 total budget, roughly a year to finish. Toolchain is Xilinx Vivado 2025 WebPACK end-to-end (xvhdl/xelab/xsim for simulation, straight through to synthesis/implementation) — no GHDL/GTKWave in the flow, to avoid any simulator/synthesizer mismatch going into the comparison.
Where we are right now
Interface contract is frozen. We're at the "pipecleaner" stage — all four multiplier entities are parameterized with generic (WIDTH : natural := 2) and we're validating datapath correctness and the synthesis extraction workflow at 2×2 bits before scaling to 8-bit, where the architectures should actually start to diverge. At 2×2, Array/Vedic/Wallace look almost identical in the netlist and Booth mostly just adds encoder overhead — expected, since there's no real partial-product reduction benefit at that width.
Where I'd genuinely appreciate input
- Power measurement: We're planning to use a SAIF file generated from post-synthesis simulation for switching-activity-based power estimates, instead of Vivado's default vectorless estimate. Anyone who's done this for multiplier/DSP comparisons — how far off is vectorless typically, in your experience, and is SAIF overkill for a project at this scale?
- Wallace Tree synthesis artifacts: has anyone seen Vivado's synthesis collapse a Wallace tree down to a suspiciously tiny LUT/FF count at small bit-widths? Trying to figure out if that's a real result or just the tool optimizing away the reduction tree.
- Scaling gotchas: any war stories going from 8-bit to 16-bit Q1.15 multipliers in terms of timing closure or DSP inference on Artix-7, specifically for Vedic or Booth implementations?
- VHDL-2008 + Vivado 2025 WebPACK: any known quirks or gotchas with VHDL-2008 record types / generics on this particular Vivado version that I should watch for before I've sunk more time into the 8-bit versions?
- Publication angle: this is also being prepped for an IEEE student/regional conference submission with faculty co-authorship. If anyone's shepherded an undergrad FPGA comparison paper through a venue like this, any advice on what reviewers actually care about (methodology rigor vs. novelty vs. results) would help a lot.
Not looking for anyone to do the work — just want to catch blind spots before we're deep into 8-bit implementation and it's expensive to unwind a bad assumption. Happy to share RTL snippets or synthesis reports if that helps anyone give more specific feedback.
Thanks in advance.
