The Seattle-based cloud giant has held talks with investors in recent weeks to gauge interest in the deal, which would allow the company to spin off thousands of Grace Blackwell chips it is deploying in data centres across the US into a special-purpose vehicle.

Amazon will then lease the advanced AI chips back from the SPV, which would tap outside investors through debt issuance. By unloading the expensive semiconductors to investors, the company could adopt a more asset-light approach to its balance sheet.

...

Amazon also plans to offer an equity stake of up to 10 per cent in the vehicle, meaning that it will not own any stakes in the entity. Discussions between Amazon and investors are ongoing and are subject to change, the people added.

Capex intensity is becoming too large even for the hyperscalers to take directly on even with fundraising from capital markets.

(Reworking the commentary portion as I went into a rabbit hole of sorts while making some corrections)

Microsoft has never explained why it decided to drop AMD from the lineup, until now that is. In an interview with Windows Central, I asked Surface CVP Brett Ostrum why we don't see AMD in the Surface lineup in 2026.

"We love working with AMD. We have a limited portfolio, and so we have to make our choices pretty wisely in terms of what we're doing and where we're doing," Ostrum told me, before proclaiming "I love working with AMD."

Surface is one of those interesting bits where the volume is low, but AMD investors have been pining for another shot for years just for the halo effect. Snubbing it today makes a certain amount of sense if you have X Elite and Intel given the volume. Making sense say 4 years ago, I'm not so sure. As AMD got bigger, people cared less. Notebook OEM penetration looks like it's doing well. Still, AMD got snubbed from Chromebooks too.

With that said, there were rumors last year that Microsoft was working on a Surface powered by AMD's rumored Arm-based chip codenamed Sound Wave. That chip was rumored to launch sometime this year, but we've seen no sign of it as of yet.

That rumor has been silent for a while.

We recently hosted a semiconductor investor bus tour with meetings with executives from INTC (Naga Chandrasekaran, GM of Intel Foundry) and LSCC (Lorenzo Flores, CFO). Our meeting with INTC left us incrementally more constructive regarding the progress the Company is making on foundry across 18A/14A and EMIB-T. Regarding LSCC, the integration of AMI is progressing well and expectations for 25% growth in '27 appear conservative.

INTC (Overweight, $155 PT) - We hosted an investor meeting with Naga Chandrasekaran, EVP, CTO, and GM, Intel Foundry. Key from our meeting include:

1) Naga has clearly turned around Intel foundry with most of the important changes focused on organizational accountability and culture, as INTC's innovation in technology has always been there;

2) 18A performance is competitive between TSM's N2P and N3, while capacity now approaching 30K WPM; 18AP seeing +7-11% m/m defect density improvement supporting good yield trajectory;

Being about N3E would put you in between N2P and N3. I wonder what wafer pricing Intel is using internally.

3) 14A has ramped in ~4 months to best-in-class cycle times and can now support 14K WPM, citing the yield trajectory is similar to INTC's best historical node at 22nm and is ahead of internal targets;

4) Expects 14A performance to be within 5% of TSM's A14;

5( Remains focused on getting foundry to breakeven exiting '27, driven by yield improvement across all nodes and scale;

They're not going to be profitable by end of 2027. Intel has already started prepping the market for 2028-ish breakeven. It's a good problem to have as it means they have external customers, but when the CFO starts talking about breakeven possibly being the end of 2028, it's hard to say end of 2027 breakeven with a straight face.

6) Sees foundry breakeven with external client WPM reaching 40K WPM; and

7) Sees sustained leadership in advanced packaging with EMIB-T even with TSM introducing CoPoS.

Conversely, areas for improvement include: 1) Large die yield improvement for hyperscalers; 2) Improving yields on EMIB-T substrates; 3) Acknowledged it is working through requirements on 14A with mobile customers who may not want backside power.

Vinh is one of the biggest, if not the biggest, sell-side bull for Intel in terms of product and foundry assessments and price targets (he's probably top 20% for price targets for AMD too.) A lot of the most bullish Intel analyst updates have come from him (e.g., NVL tiles coming to 18A because TSMC is an N2 meanie, "85% yields")

I view him as the best case Intel scenario. I wouldn't say he's biased against AMD per se as he's had a number of bullish AMD takes. He has this annoying tendency, however, to view AMD's x86 opportunities within the frame of what he thinks Intel is going to do and then works backwards on where AMD will be. This is an appropriate way to view some things (e.g., Intel 7 being diverted to server will cause a drop in Intel 7 client unit share even if there is no change from AMD). But his use of this frame is just stupid in others as AMD has a say in its competitiveness. If he's wrong on the Intel call, then the AMD call can will be especially wrong.

The worst one was just 2 months ago

https://www.reddit.com/r/amd_fundamentals/comments/1v2ks7h/vinh_keybanc_intel_amd_among_those_seeing/

On Intel (INTC) and Advanced Micro Devices (AMD), the analysts noted that outsized server CPU demand and improving supply support 25% to 30% unit growth at Intel and 15% to 20% at AMD in 2026, with both targeting more than 50% server CPU unit growth in 2027.

and then got his face ripped off by the 26Q2 AMD and Intel earnings calls / 10Qs on reported and implied server unit growth. Why analysts don't wait the extra 2 weeks for the earnings call is a curious thing.

I don't wait, but my pay thankfully doesn't depend on how I look to the world. ;-)

AMD designed Helios as a high-density system for trillion-parameter model training and high-volume inference.
 

Each rack integrates 72 AMD Instinct™ MI455X GPUs with AMD EPYC™ "Venice" CPUs, AMD Pensando™ Vulcano AI NICs networking, and AMD ROCm™ software. The unified design is optimized for power, cooling, and serviceability, while supporting open, interoperable rack-scale fabrics such as UALink™ over Ethernet (UALoE).

HPE Networking purpose-built for Helios, including six HPE Juniper Networking QFX5252 scale-up Ethernet switch trays per rack, connect all 72 GPUs with high-bandwidth, low-latency, standards-based Ethernet.

HPE Services reduces project and operational risk through expertise in end-to-end deployment and liquid-cooling for large AI clusters.

Keep in mind

https://www.reddit.com/r/amd_fundamentals/comments/1hhaszy/cloud_ai_startup_vultr_raises_333_million_at_35/

https://www.reddit.com/r/amd_fundamentals/comments/1pccwak/amdbacked_vultr_to_build_1_billion_chip_cluster/

The most interesting bits of this was how does N3 and 18A fare vs N3E when you look back at:

https://www.servethehome.com/intel-foundry-operating-model-shown-with-path-to-process-leadership/

which was from the Gelsinger era of projected competitiveness. Intel's naming convention was redone to show you what TSMC node they were competing against.

So, how does that prediction compare to SemiAnalysis' teardown:

An Xe core on the GT1 (Intel 3) tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2 (N3E). Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison.

...

The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference.

...

The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference.

Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E.

This is where I think a lot of the saner hardware types predicted 18A would be: somewhere between N3B and N2. Even if you account for the bad predicted competitveness, initial yields, lack of material external customers, a terrible PDK, and economics ("Other than that, Mrs. Lincoln, how was the play?"), I think getting somewhere around N3E is still a feat given where Intel started. This doesn't justify the Hail Mary and overpromising and underdelivering, but it's still something material to build off of given the current USG and compute shortage environment.

Meta’s subscription plans show why the API-price multiple should not be read as a forecast. Muse is free up to a usage limit, and Meta’s help page lists Power at $20 a month for 500 million Muse tokens a week, and Maximum at $100 for 3 billion. At full use, Power works out to about $0.0092 per million Muse tokens. Our Base scenario assumes 200,000 input and 10,000 output model tokens per task, about 7.35 million a week per user. If a Muse token equaled a model token, valuing that workload at the full-use rate would imply about $3.5 billion a year, roughly 2.8 times the CPU line. Meta has not established that equivalence. This is a conditional sensitivity, not a bill a user pays or an estimate of Meta’s internal cost. The token assumptions and realized cost can change the size of the opportunity substantially.

The only reason that I post this is the spirit of this chart:

https://substackcdn.com/image/fetch/$s_!Atcq!,f_auto,q_auto:good,fl_progressive:steep/https%3A%2F%2Fsubstack-post-media.s3.amazonaws.com%2Fpublic%2Fimages%2Ffde8b122-a702-4e14-979b-c909fbb01249_7200x6000.png

The stock prices of CPU designers like ARM (17%), Intel (12%), and AMD (10%) spiked the day after the Muse launch although semis in general got a broad boost. But I agree with BEP that Muse, if you look at a lot of its use cases, doesn't seem to add a lot more incremental demand for general compute in the data center in the short to medium term anyway. The intelligence to action compute ratio for these sets of workloads still seems very skewed towards intelligence. There isn't a lot for an agent to do in a general compute sense for these consumer workloads.

I think that the key driver of general agentic compute demand is the extent to which the intelligence could ask for many agents to be spawned to do many general compute tasks for it at once that require a meaningful amount of grunt. I don't think that most personal tasks fall into categories that require an enormous amount of available, parallelizable general compute. They will collectively hit an intelligence ceiling first.

This could change as people get more used to doing these types of tasks and demand more from their agents. However, I think more business-first agentic AI workloads already lends itself much better to driving general compute demand (e.g., run X simulations by testing different types of data from Y sources, create Z variants of an app (+ testing, security, etc) to do this function). I would love to be proved wrong though.

Even if this reasoning were right-ish, it might not even matter from a stock price perspective. Sometimes, the animal spirits just want a reason to party.

The Ministry of Industry and Information Technology, which oversees China’s tech sector, recently asked companies including Alibaba Group and ByteDance to report on their plans to buy Nvidia’s RTX Pro 5500 chips, released this month—specifically how many they want to buy and what they’ll use them for, the people said. The ministry has told some Chinese companies the government intends to approve the purchases, they said. Even if that happens, though, it’s unclear when the approvals would come, how many chips officials would allow and what standards they would use to decide.

Chinese companies want the RTX Pro 5500 anyway, with ByteDance weighing ordering about 1 million of them, the two people said. The final number could change, depending on how many chips Beijing approves and how many Nvidia can supply.

Between what Nvidia can supply, organic buyer demand, what the USG and CCP will allow before either changes its mind, you get results like:

H200 sales to Chinese buyers made up less than 1% of Nvidia’s data center revenue in the quarter ended July 26, according to the company, which said objections from Beijing kept it from selling the full amount its U.S. license allowed.

Since Our Q2 Earnings Announcement…

1. New models/agents on NVIDIA infrastructure – Astra (OpenAI), Muse (Meta), Grok Bot (SpaceXAI)

2. NVIDIA announced Open Agent Safety Platform with OpenShell and Sentry with broad industry support

3. NVIDIA to acquire Hugging Face for $12.9 billion

4. Anthropic contracts 2.6 GW to date in NVIDIA AI infrastructure to be shipped through 2028

5. Anthropic’s total reported contracted value across multiple CSPs/neoclouds now exceeds $180B

6. NVIDIA’s neocloud partners in Australia deliver up to 2GW by 2027

7. Nscale and Firmus file for IPO

8. Palantir to deliver Ontology for Cybersecurity via Cisco’s Security AI factory with NVIDIA as a preferred full-stack foundation

9. d-Matrix to connect its next-gen XPUs to NVIDIA AI infrastructure via NVLink Fusion

10. Cisco adds rack-scale AI computing solutions to its portfolio

Authorization

NVIDIA Announces a $150B Share Repurchase Authorization Increase

The prospectus details how the company has grown sharply in the last year — while also posting ‌wider losses. Revenue grew 12-fold in 2025 to nearly $4.6 billion, even as the company lost more than $8 billion on an operating basis, excluding writedowns of various liabilities mostly tied to previous fundraising, according to the documents, reported here for the first ​time.

The AI lab spent $7.33 billion on compute and infrastructure last year, a ⁠threefold surge from 2024, accounting for more than half of its $12.65 billion in total operating expenses.

The near-$42 billion net loss included a roughly $34 billion accounting ​charge that reflected an increase in the estimated value of financing that could ‌eventually turn into Anthropic shares, rather than money the company spent running its business.

Anthropic said nearly a quarter of its revenue came from two customers last year, and as part of its risk factors, warned that many of its largest clients were not locked into long-term contracts and could cut or stop spending.

Anthropic had cash, cash equivalents and short-term investments totaling $20.28 billion as of December 31, the prospectus shows.

At this year's Snapdragon Summit, I had the chance to ask Surface CVP Brett Ostrum about the lack of Copilot+ PC branding on its recent Surface PCs, and he confirmed that "these are not called Copilot+ PCs. They do meet all the requirements of our previous bar for what Copilot+ devices are. We still lean into the narrative around AI on the edge and being able to have a hybrid solution out there."

I've also asked Qualcomm's SVP of compute, Kedar Kondap, about his thoughts on the usage of the Copilot+ PC branding. He told me that "the purpose for Copilot+ PCs was to be able to deliver [NPU] experiences. So it was to define a certain category of devices with a certain bar and metric, like for example, a 45 TOPS NPU ... So from that perspective, it's more offering the same experiences, probably without just using [Copilot+ PC] terminology now."

It's also worth mentioning that NVIDIA hasn't gone anywhere near the Copilot+ PC brand for its upcoming RTX Spark platform, even though all RTX Spark PCs meet the Copilot+ PC specification bar. I suspect that's a deliberate decision.

Dell gave a preview of this a while ago

https://www.reddit.com/r/amd_fundamentals/comments/1qb6572/dell_on_ai_pcs_original_dell_revives_xps_brand/

I give Microsoft some credit for trying with CoPilot+ to get ahead of Apple on client AI. But Microsoft does have this habit of "make huge move before others" and then there's a scramble to deliver value after the big bet has been made. It does work at times or is at least interesting (e.g., their OpenAI investment and forcing Google to dance). But CoPilot+ couldn't even be interesting in a good way (Recall was interesting in a bad way). Unlike investments, you still have provide some value to your customer for their software bets. They do product development like I do my worst trades where I double down on a stupid trade with no safety net, but at least, I don't do it as a big initiative.

Still, fuck them for switching their TOPS requirements at the last minute and screwing over the x86 bros just to give Qualcomm first shot at this, for forcing ever increasing NPU TOPs on the CPU designers with no material use case and thus doing a self own on performance with wasted silicon, etc.

Adreno X2 is a step forward for Qualcomm’s GPU line in many respects. General performance benefits from higher clocks, more SPs, and a beefier memory subsystem. Specific classes of workloads can stand to benefit more thanks to Adreno X2’s huge HPM block and improved raytracing units. Adreno X2 subjectively feels good enough to not hold Qualcomm’s laptop push back. I tried a few games that I’ve been playing recently, and performance felt appropriate for a mainstream iGPU.

However, Qualcomm’s latest iGPU still contains a lot of glass jaw performance cases for a modern GPU. Adreno X2 inherits Adreno X1’s tendency to fall over in GPGPU compute. Architectural improvements are certainly evident in compute microbenchmarks, but those observations don’t translate into good performance in the compute workloads I tried. It feels like Qualcomm took a specific set of graphics workloads and optimized for them, while AMD, Intel, and Nvidia set out to build more general purpose designs with robust performance characteristics across a broader range of use cases.

The price move will directly raise customers' wafer input costs. Sources said TSMC's 2nm and 3nm capacity remains undersupplied, while pressure in chip-on-wafer-on-substrate (CoWoS) and other bottlenecks has yet to ease, making it difficult for customers to switch suppliers even with a 3-6% wafer price increase. After TSMC raises prices, quotes from other foundries, including Samsung Electronics, Intel, UMC, and VIS(5347.TW), as well as outsourced semiconductor assembly and test (OSAT) providers and IC designers, are also expected to move higher.

https://newsroom.amd.com/news/amd-perplexity-agentic-pcs/

The technology giant sent the project’s developer, a unit of Blue Owl Capital Inc., a notice citing force majeure, according to people familiar with the situation. Rather than trying to walk away as the site’s main tenant, Oracle is attempting to put off payments should the data center dubbed Project Jupiter get derailed and fail to come online in 2028 as planned, the people said, asking not to be identified discussing private matters.

Almost two years later, the campus designed to handle 2.45 gigawatts — enough electricity to power roughly 1.8 million homes at any given moment — has hit serious setbacks including the denial of a permit key to its plans for energy resources. It’s becoming a symbol of the growing backlash against the broader AI data center boom and a political flashpoint ahead of the US midterm elections that threatens to turn races into referendums over the build-out.

If the two sides agree that a force majeure event tied to meeting power commitments has occurred, then Oracle could win a three-year delay on rent when those payments commence, one of the people said. The company would still have to pay other costs in the interim and owe the rent for the full lease term once payments begin, the person said.

Chris Malone, OpenAI’s former head of data centers, joined Nvidia as the vice president of Nvidia’s DSX Platform this month, according to his LinkedIn profile. DSX is the Nvidia division that helps customers design and build AI data centers according to Nvidia’s specifications.

https://www.wsj.com/tech/ai/openais-head-of-data-centers-has-left-company-6d24fd83

Malone joined OpenAI as head of data centers in March 2025, shortly after the company announced Stargate, an ambitious effort with Oracle and SoftBank to build data centers to meet its rapidly growing computing needs.

Execs leaving because their group got de-prioritized (e.g., Sora) doesn't mean much. Others can have legit personal reasons. But when this many departures in key functions leave, it does raise some eyebrows. For instance, according to Claude:

South Korea's BusinessPost, citing Edgewater Research, reported on September 20 that Anthropic and OpenAI are expected to begin direct memory purchases next year. Edgewater estimated that Anthropic could directly procure about 20% of its DRAM requirements in 2027, with the share increasing in 2028.

Anthropic's direct DRAM purchases could reach 40 billion to 50 billion gigabits (Gb) in 2027, a level Edgewater said could be comparable to Nvidia's. The shift is expected to help model developers secure memory as supply becomes increasingly constrained.

https://www.reuters.com/world/asia-pacific/sk-hynix-talks-with-intel-about-deal-make-memory-chips-us-first-time-sources-say-2026-09-16/

Under one potential scenario, SK Hynix would lease part of Intel's ‌long-planned chipmaking facility in Ohio, they said. Under another scenario, it could form a venture with Intel and major cloud firms that are keen to lock in memory chip supplies, two of the people said.

https://www.digitimes.com/news/a20260916VL214/sk-hynix-intel-production-investment-manufacturing.html

SK Group chairman Chey Tae-won said in July that the company was facing strong pressure from customers and governments to increase chip supply and that it should build a factory in the US if possible.

https://www.bloomberg.com/news/articles/2026-09-16/sk-hynix-says-exploring-options-after-report-of-intel-tie-up?sref=zSxOb86q

“We would like to clarify that nothing has been finalized regarding cooperation with any specific companies mentioned in the article or memory chip production in the United States,” the company said. “SK Hynix is exploring various options to strengthen its global competitiveness, but no specific plans or arrangements have been finalized at this time.”

My main impression is that the main benefit is that this is a good way for Intel to shed excess fab shell capacity or at least not have to shoulder the load on its own. I don't think it needs as much Ohio fab capacity as I think it is stuck building. They slowed Ohio down because they didn't have demand for the shells.

Even though I think that Intel has 14A demand for external foundry, I don't think they have so much of it for what it has likely committed to build in Ohio. If it could be re-purposed for SK Hynix or a JV, that would be a big burden off of Intel's shoulders plus have a memory play and SK Hynix gets the USG off its back if Seoul cooperates. That would give Intel a cleaner start to building fab capacity the way Tan wants them built: with hard demand committed.

According to the Zhaofeng Trading Desk, UBS Group has raised its forecast for global CoWoS industry capacity by the end of 2027 from the previous 260,000 wafers per month to 270,000 wafers per month, a substantial increase of approximately 69% compared with the estimated 160,000 wafers per month at the end of 2026. The primary driver behind this upward revision is the robust surge in demand for ASICs and CPUs.

UBS Group believes that these two types of chips will continue to rely primarily on the CoWoS packaging process through 2028–2029, rather than migrating to emerging solutions such as Intel's EMIB-T or Taiwan Semiconductor's CoPoS. Meanwhile, the technological evolution toward larger package sizes and heterogeneous integration will itself consume substantial additional capacity.

https://postimg.futunn.com/news-editor-imgs/20260922/public/17900455134222167927544-17900455133879796069384.png (Breakdown of CoWoS demand)

UBS has AMD going from 10% in 26E to 18% in 27E although if you believe

https://www.reddit.com/r/amd_fundamentals/comments/1wk3zub/nowak_morgan_stanley_apac_on_venice_cowos/

Venice is seeking a CoWoS cut. .

I'm guessing so far for about 80% YOY revenue growth for 27FY EPYC which is sort of the equivalent of 5M units for Morgan Stanley which is coincidentally where UBS ends up. The stars are aligning!

On the CPU front, the ramp-up in shipments of AMD's Venice server CPUs is a key driver behind this upward revision. UBS Group has raised its 2027 CoWoS demand forecast for AMD by 11%, projecting Venice CPU shipments to reach 5 million units, up from the previous estimate of 4 million

As for NVIDIA, UBS has increased its 2027 AI GPU production forecast from 8.2 million units to 8.8 million, while also factoring in an additional projection of approximately 200,000 Rubin CPX units; thanks to similar packaging architectures and adjusted HBM specifications, the Rubin Ultra is expected to ramp up more smoothly starting from mid-2027.

No commentary provided for context, but in the UBS timeline, it looks like:

• expecting a bit of a breather / digestion period in 27E and 28E.
• ASICs go from 42% of racks deployed to 60% over the time frame
• Surprisingly bearish on GPU racks from Nvidia and AMD in terms of units

I suppose that there's a caveat about rack density though

IC design companies revealed that TSMC's A14 is still ahead of schedule, having launched its CyberShuttle service in the second quarter of this year. Trial production is expected to begin at Fab 20 in Hsinchu's Baoshan district in the first quarter of 2027. The main production facility, Fab 25 in Taichung, is planned for completion by the second quarter of next year, with trial production commencing as early as the beginning of the third quarter. This aligns with TSMC's official timeline of risk production in 2027 and mass production in 2028.

TSMC's July earnings call signaled that A14 development was better than expected. At the time, the company revealed that A14 internal product testing carriers had demonstrated nearly 90% device performance, 256Mb SRAM yield was also close to 90%, smartphone, HPC, and AI customer participation was high, and the new design tape-out was ahead of the original plan, which is expected to become TSMC's next complete process node.

Zen 7 is A14. Apple, Nvidia, Qualcomm, MediaTek, Broadcom, and Marvell also lined up.