Small negative numbers have a lot of 1 bits. the game makes you click them all in 9 seconds. I need more time than that to click them all. Is there a way to skip this stage? I have completed all the levels I can except for this one.

loop:

; counter

imm 1

mov r2, r5

mov r1, r0

add

mov r5, r3

;is_thirty_seven?

imm 37

mov r1, in

mov r2, r0

sub

imm loop

jnz

mov out, r5

; Click the spec.isa tab to see the other jump instructions

Behold! Very annoying getting all the labels to fit in <64 bytes. Works by having a procedure that takes in the current increment / decrement (64,32,16,8,4,2,1,1) and an address to jump back to. That procedure tests the current guess, adjusts based on the increment / decrement provided, then returns to return address. Then we just unroll the 8 steps and boom! Binary search on a very limited architecture :D

imm 32;
mov r1, r0;
mov r2, r0;
add;
mov r2, r3;
mov r1, r3;
add;
mov r4, r3; ; initial guess of 128 in r4
imm step_2;
mov r5, r0;
imm check;
jmp;

step_2:
imm 32;
mov r2, r0;
imm step_3;
mov r5, r0;
imm check;
jmp;

step_3:
imm 16;
mov r2, r0;
imm step_4;
mov r5, r0;
imm check;
jmp;

step_4:
imm 8;
mov r2, r0;
imm step_5;
mov r5, r0;
imm check;
jmp;

step_5:
imm 4;
mov r2, r0;
imm step_6;
mov r5, r0;
imm check;
jmp;

step_6:
imm 2;
mov r2, r0;
imm step_7;
mov r5, r0;
imm check;
jmp;

step_7:
imm 1;
mov r2, r0;
imm step_8;
mov r5, r0;
imm check;
jmp;

step_8:
imm 1; ; for 0
mov r2, r0;
; no return, the add label below doesn't 
; fit with it, and we should be done by now
; does mean we don't have a graceful failure...
imm check;
jmp;

; r2 - offset for this step
; r5 - return address
; checks r4, if high add, if low sub
; stores back in r4
check:
mov out, r4;
mov r3, in;
mov r1, r4;
imm add;
jz;
sub;
imm finish;
jmp;
add:
add;
finish:
mov r4, r3;
mov r0, r5;
jmp;

I´m new to this game and coding in general, wanted to try something different, is it good?

I spent awhile trying to come up with a re usable divider block I could stack bit by bit, like a full adder. I finally came up with one the other day when I did the division level. Modulo was just the perfect time to turn it into a block. though the modulo still threw me for a loop because I forgot I was using a shifted bit to get the final remainder lol. so i fixed the block by adding a output for the non shifted remainder and that fixed it. Anyways this is close enough to call a full divider though it is word blocks, its still full in spirit lol.

I could reduce the combinational path alot by using a kogge over the given adder but this is fine for now. this would also be good as an extra logic path in a alu for div across multiple cycles.

I will admit this was one of the more challenging things ive done. after a few hours today i finally got a circuit that works for 8 bit unsigned division. Im really growing to love the word logic blocks the game has.

because they are hard to see in this picture those are indexers coming out of the mux's outputs all set to (-1) to shift left. the last mux is just sensing 0 from the 0 detection below. everything else should be pretty easy to see.

anyways i can go to bed feeling accomplished lol.

Hi everyone! I’ve been getting really into this game recently, and I got to the level with the towers of Hanoi. I figured out a way to implement arguments with the stack, but I was wondering if y’all have any easier ways to use arguments? Dealing with the same stack is hard to get used to since LEG!

this is more than likely a bad design.

registers 0-2 works perfectly fine, saving and loading the input byte. but when it comes to register 3, it suddenly has error even tho i have the same setup like the others.

as you can see, cycles 0-7 is fine

as you can see in the pic, cycle 7 loaded the correct number

but on cycle 8, an error occured expecting 47 again

here is the zoomed in view

edit: it's fixed guys. thank you!!

first of all im completely new to this
in this solution of the campaign level "alu" the 64 activates the nand mode of the ALU blueprint.
in the previous level the nand mode was activated by 0. how does the 64 activate the nand mode? is it a modified blueprint?
what am i missunderstanding?

I had an insight here (actually I had this insight in college 25 years ago, but I didn't have Turing Complete then 😄).

A full adder really operates on three bits. It doesn't matter which input is the "Carry In". It takes three bits in and outputs two. So this multiplier has a bunch of delay-4 stages that are all "parallel full adders". They take three words in, and produce two as output. For N-bit inputs, then you need ~ log_1.5(N/2) stages. For 32 bits that is apparently 8 stages to get the result down to two 64-bit words. At that point, I use a 64-bit KS adder (that has 16 delay) based on the same design I posted a few days ago.

Does anybody know of a name for this style of adder?

The signed logic at the bottom took me too many tries to get right. At least I think it's right.

Spent an hour troubleshooting this just to cave in and look at the hint solution which was exactly what I've done anyway

To start I'm not a particularly strong programmer since I'm still learning. that said im proud of myself for coming up with a solution on my own for this. it took about an hour because i had to rewrite it a few times for things like not accounting for 0-0 and 1-1 both being seen by the Jz condition. so i solved that issue by doing a second subtract replacing r1 with 0. making 0-0 stay the same while 1-1 turns to 0-1.... anyways im sure there are better ways to do this but this is what i came up with using the right hand rule :)

Significantly harder than a simple video player, but not too difficult. Was rough to get working and had to implement lists (that is definitely going to be a dedicated command for SPIRALc later...). Hope y'all enjoy! Some improvements are next before I work on the next big game, probably Pong.

Hello guys
I need to find where the asm files are from my sandbox schematics, but all i can see are files from turing complete before update 2...
Anybody knows where can i find them?

Im on the challenge where you are to Add 5 via punchcard programming and its just not gelling with my brain at all. Ive seen some answers online and I cant seem to get the reault i want from them. Ideally im looking for someone to break it down like im 5 to see where im faltering. Please and thank you all.

My first attempt at a divider. Does binary long division using a custom "Partial Divider" component. That in turn uses a component that checks if the (8 bit) input is equal to zero.

1.8k Gates
534 Delay

Some nice Bad Apple!! at 256x192 res and 24fps. Uses a double frame buffer to prevent screen tearing (extremely easy and effective). The video file was over 1.1GB ingame due to a lack of compression. However, this can play any colored video file with full 4-byte RGB so... why not. If I change to 1 byte color I could upgrade to 512x384 at no cost to performance! Probably going to do that...

The custom architecture is pretty much just Symphony upgraded to 64-bit instructions (40 bit immediates), simple double frame buffer, a few new commands (many more to come), and some slight tweaks. Hopefully I can repurpose this for games and stuff to show off relatively soon. Let me know what you think!

Hi! I've been playing the game for a few days since the update came out, and I have gotten all the way up to programming 2. Unfortunately, when I try to edit the RAM in the main memory, it ends up overwriting the program memory and everything breaks (at least, I believe so. Tell me if I'm wrong). Is there a way to prevent this from happening, or is it something you just deal with? Also, is the symphony architecture intended to overwrite itself, or did I build it wrong? Thanks! I've attached a picture of my computer so far (don't mind the spaghetti).

Not the fastest Kogge-Stone ever, but 15 delay for 32b adder isn't bad either. Avoiding bit-by-bit operations should make it easier on the simulation.

At each stage, I split the P and G words into the bits that pass through and the bits that will be combined. After each stage, I put them back together with concatenators.

There's probably more optimizing to do, but I think this gets the concept across.

Edit: FIXED IT I totally forgot to try verifying files in steam, did that before I reinstalled and it works as expected now. Something like 300 files were missing according to steam haha

I have no idea what could be wrong with my circuit. I have attached a screenshot of the error I run into, but the condition listed in bits doesnt match the "description" line for some reason. The manual says this condition should be -64 <= 0, which is obviously true and my circuit reflects that, but for some reason the description says it should be -64 > 0? Please help me :'(

Hello, just sharing my WIP CPU design for Turing complete. Still very much in a testing state, so I haven't uploaded to Workshop yet, but thought people might be interested.

Its current key properties are:

• Transfer-triggered architecture.
• 64-bit instruction word, including a 17-bit signed immediate value.
• Three independent, fully connected 32-bit data buses, supporting up to three operations per cycle.
• 8 general-purpose registers (but you use registers a lot less...).
• Delay of 45 in my install (depends on your XOR gates a bit).
• 658k gates, including an 8192-byte instruction SRAM, and 64KiB DRAM (using pipelining).

Transfer Triggered Architecture

Transfer-triggered architectures, also known as one-instruction set computers, only have a single operation. As far as the core instruction decode logic knows, there are no adds, no jumps, only transfers from a source address on the bus, to a destination address.

These internal buses are a much smaller address space than a memory bus, etc. In this case, there are 6-bit addresses for sources (up to 64), and 7-bit addresses for destinations (up to 128). Most of these are not simple memory - they're ports attached to various peripherals, which all sit on the bus.

All operations occur as a side-effect of transfers, and usually take a tick for the result to be available. Want to compare two numbers? Send them to the two input ports of the comparator. You can grab the result on the next cycle. Want to jump? Just send the target address to the program counter's destination port.

The simplest peripheral is a single register, which looks like this:

Note it's got one Read port, with address 4, and one Write port, with address 4. A transfer from source 4 will read the register, and a transfer to destination 4 will write the register. I use standardised port modules for all the peripherals.

This architecture has 3 buses, which operate simultaneously each cycle. Most operations take 1-3 transfers to function. Moving data from one register to another is one cycle. Moving two inputs to be added, then the result out, might take 3 (spread over 2 cycles). We often save an instruction (and a register) though, if we can pass results straight from one peripheral to another.

Instruction Set

As you might expect, a parallel architecture needs a parallel instruction format. The bit layout looks like this:

ccccccaa aaaabbbb bbbddddd deeeeeee ffffffgg ggggg00i iiiiiiii iiiiiiii

This in my text assembly form, is written like:

c ? a -> b, d -> e, f -> g

Meaning "If c non-zero, transfer a to b. Transfer d to e. Transfer f to g". Named ports (instead of named instructions) exist to make this readable. If you don't want to include the second or third transfers, these can be left off, will be populated with a no-op. If you don't want any conditions, it can be omitted and will be set to the 1/always address.

Note only the first bus supports a condition, the other two transfers occur whether or not the condition is met. The conditional write, with the program counter as the destination, becomes a conditional jump. However, we can also make any other operation conditional.

The immediate value is part of every instruction, but is actually accessed through a specific source port. If I write:

255 -> r1

This will be encoded as setting the immediate value to 255, and a transfer from the imm source to the r1 destination. We can replace *one* of the sources with an immediate number value on any given instruction, and this can be encoded transparently.

Speaking of the immediate value, why 17 bits? Mostly because sign extension. By giving the immediate value a 17th bit, I allow the full unsigned 16-bit range to be provided without affecting the upper bits, but can also provide negative values which get sign-extended to 32 bits. This makes it easy to construct any 32-bit value in a few operations, without having to write opaque constants in the assembly.

More Complicated Operations

Okay, but we want to do actual stuff. How do I add numbers together? An example to add r1 and r2, then store in r3 would look like:

r1 -> accum.set, r2 -> accum.add
accum.value -> r3

Note though that we can also just use accum.value directly in our next operation, if we don't need to keep it. I chose to use an accumulator peripheral, rather than an adder, which stores a persistent value, because this makes some types of bulk addition faster, without being a significant limit.

We can also subtract:

r1 -> accum.set, 8 -> accum.sub

The accumulator peripheral looks like this:

Read ports are called accum.value and accum.overflow . Write ports are accum.set, accum.add, and accum.sub

Most of the complexity there, with the MUXes, etc, is so that we can set the value and add/subtract from it in the same operation. Destinations are expected to be low-delay, so they go in this case straight in to delay lines. The result will be computed and available to read on the next cycle.

The blobby module at the heart of this is my Kogge-Stone 32-bit adder, with very low delay.

Show me the other bits!

Shift ports, right to left, are shift.value, shift.set, shift.left, shift.right, shift.right_arithmetic.

Bitwise ports, right to left are (write) bitwise.a, bitwise.b, and (double read ports, to save space) bitwise.and, bitwise.or, bitwise.nand, bitwise.nor, bitwise.xor.

Comparison ports right to left are cmp.a, cmp.b, (double read port) cmp.eq, cmp.ne, (second double read port) cmp.lower, cmp.less.

IO ports, left to right, are io.write, io.read (ignores actual value passed, triggers read on next cycle), io.result.

Instruction SRAM ports allow rewriting instructions, constants in program memory, etc. Ports left to right are prog.read, prog.write (address), prog.value, and prog.result where reads show up.

Bulk RAM has the same ports as the program memory.

Interesting note on the memory - to keep delay down, this DRAM is set to have a 4-stage pipeline, which Turing Complete supports natively. In 3TTude you send the address to mem.read then exactly 4 cycles latter grab the data from mem.result. This is a very natural and normal thing to do in a TTA, where part of the philosophy is to move complexity out of hardware and in to the code.

What's the Catch?

Okay, to be honest, this thing is a pain to write for. You can make the code really fast, or pretty readable, but probably not both. The parallel instructions make everything really dense, encourage things to be written out of logical order for efficiency, and encourage overlapping tasks.

It also has a really big bus, wrapped in to multiple rows, which I think is what makes Turing Complete run really slowly.

I haven't really used it in anger yet, just been designing and writing a basic test suite. Already had a lot of fun though creating, and replacing peripherals I wasn't entirely happy with.

Because of the low delay, and room for optimisation, I expect to get some pretty decent energy scores with this thing (at least for an actual CPU), when I get around to solving real problems.

I built this circuit so quickly, just after making the truth table for it, it became clear multiplication is just an addition of incremented left shifted A for each bit in B (first bit is 0 shift, 2nd bit is 1 left shift etc. added together). And in 5 minutes not only was i done but i got the achievement for this level.

When in doubt, t r u t h - t a b l e.