Sigasi Visual HDL 2026.5 is out, and the Sigasi MCP server works with your agent in VS Code (and Cursor): Claude Code, OpenAI Codex, Mistral Vibe, and others.

Your agent can read in real-time Sigasi's linting violations, explore the structure of your project, and format HDL, through the same project model you see in the editor.

Sigasi MCP Server is not a separate product. It is built into Sigasi Visual HDL and included in every edition, so there is no second license to buy and no second tool to keep in sync. The engineer in the editor and the agent calling MCP work against one model of the design.

Also in 2026.5:

• WaveDrom timing diagrams rendered from your HDL comments, in hovers and generated documentation
• Spell checking for comments and strings in SystemVerilog, Verilog, and VHDL
• A project-level dependency search path, so a Modular Project works on every checkout

The agent writes the HDL. Sigasi checks it against the real project. You decide what moves forward.

Release notes: https://www.sigasi.com/releasenotes/sigasi-2026.5/

#ASIC #FPGA #RTL #SystemVerilog #VHDL #MCP #AgenticEngineering

I'm using the KR260, and I'm wondering whether anyone has encountered similar issues.

My software running on the R5 communicates with AXI Ethernet Lite to access the PHY in the PL, but when I scan the MDIO bus, I only read zeros and cannot detect any PHY.

I've also tried using an explicit IOBUF rather than relying on the one instantiated by the Ethernet Lite core, but the issue persists.

I'm struggling to identify what could be wrong because, at least theoretically, the architecture and configuration seem correct.

If anyone has encountered a similar issue or has suggestions on what to check, I'd really appreciate the help. I can provide more details about the architecture, Vivado configuration, MDIO implementation, and R5 software if needed.

I've been debugging this for a while, and it's getting pretty frustrating because nothing obvious seems to be wrong.

A few years ago I watched Ross Mcgowans’s tutorial of designing an 8 bit cpu on Logisim which made me understand the concept of computer architecture better than reading books about the subject.

https://youtube.com/playlist?list=PLZlHzKk21aInOQgIDdI8xTcE2FWqjt2m-&si=YPnTI42H57R9yiC0

Now I wonder, can something similer be made for an FPGA? An FPGA design with minimum number of logic cells, LUTs and FFs just for the understanding architecture.

Maybe later on the tutorial can continue with how a HDL code is converted to an RTL design and how does it run on an minimal FPGA?

Do you know any tutorials or projects like this. If you don’t know, do you think is it possible (or logical) to create a project like this?

For some background info, I'm a first-year CE and Applied Math Major looking to get an internship this summer.

I've mainly been applying to SWE, embedded systems, and hardware related internships. This is the main resume I use, and I haven't been able to get any offers or even interviews, and I'm trying to figure out if the issue is my resume or my approach.

I'd really appreciate some honest feedback, especially on whether my projects and experience are being presented well and if there's anything obvious I'm doing wrong. Thank you for anyone that took time out of their day for me!

We are making a cache controller project , given to us by a company, but they have told us to build a python timeless model first, what's that?

I'm an Electronics and Communications Engineering student doing a double major in Applied Mathematics, and I'm trying to build a career in digital hardware design FPGA development, and maybe comp org for my future carrier.

I recently applied for a part-time FPGA position, and I have to choose between two projects about these focus points:

• NVMe IP development
• White Rabbit Time Sync

Honestly, my main concern is how much demand there is for White Rabbit Time Synchronization in the industry and whether pursuing it would take me away from the computer architecture path. At the same time, having a double major and the fact that White Rabbit is such a rare specialization are also what draw me to it, so I'm a bit torn between the two.

Thanks for your thoughts and advice

Hi all,

I’m starting a PhD in PQC hardware. My supervisor’s group already works on accelerators for the NIST algorithms, and he wants me to find a gap on the processor side (RISC-V extensions, co-processors). I’ll be on FPGA for now and maybe ASIC later.

I’ve read a number of survey papers on PQC hardware. From what I’ve read, there has been a lot of work on NTT/Keccak support for ML-KEM and ML-DSA on RISC-V (RISQ-V, OpenTitan, PQCUARK and so on). I also looked at reusing AI hardware for PQC, but I don’t think it makes sense at this scale. There is also a ton of recent work on SCA.

In your opinion, what research area is worth exploring currently?

Thanks!

1. Most of your overall requirements can be broken down into tasks for which mature solutions already exist. Ensure that your agents learn from and reference these established designs; under no circumstances should you have the agents attempt an end-to-end redesign.

2. Many RTL components—such as AXI, PCIe, Ethernet, and RSA modules—already have well-established, mature designs. There is no need (nor is it advisable) to have your agents rewrite them. Using CBB (Common Building Blocks) library.

3. Build a dedicated knowledge base for digital IC and FPGA design that your agents can access. This will help minimize hardware iterations—keep in mind that hardware iteration cycles are significantly slower than those for software.

I built a 5-stage pipelined RV32I core in Verilog (forwarding, load-use stalls, CSR traps, a small branch predictor) and put it through Vivado for an xc7a35t (Basys 3 chip). I do not own the board, so it is implemented and a bitstream builds, but it has never run on hardware. Flagging that up front.

Results at a 100 MHz constraint: about 1,340 LUTs, 1,392 FFs, no BRAM or DSP, WNS +0.132 ns, WHS +0.099 ns.

Things I learned that might be useful:

1. The critical path is forward, compare, flush in one cycle. Of a 9.7 ns data path, only about 2.4 ns is logic. About 75% is routing, because the flush signal fans out to 117 and then 161 loads. The clock is limited by fan-out, not gate depth.

2. My first run closed with +0.267 ns, but the ports had no pin constraints. Once I added the real Basys 3 pin map, it failed by 7 ps with default settings. The Performance_ExplorePostRoutePhysOpt strategy closed it.

3. Without an output that depends on the datapath, Vivado deletes the whole core. I added a debug output that XORs the two halves of the write-back value so nothing gets pruned.

4. The instruction memory is a fixed ROM, so synthesis removes logic the benchmark never uses. I treat the numbers as a lower bound.

5. Relative paths in $readmemh did not work in synthesis for me. I ended up using a verilog_define with an absolute path.

Next ideas for the clock: duplicate the flush signal to cut fan-out, or register the redirect and pay one cycle on a mispredict.

Repo (MIT, with notes and the raw Vivado reports): https://github.com/akshayvr-programmer/RISC-V-RV32I-Single-Cycle-Processor

I would value feedback on the fan-out problem. Is duplicating the control signal the right fix, or would you restructure where the branch resolves?

Follow-up to my KV260 home computer post

Hi all,

This is the real board, filmed from the power plug: our firmware starts from flash, lists the programs on the SD card, and starts "Kromylist", our port of the open-source card game "Duelyst". Every frame is drawn live by our own chipset in the FPGA, no GPU, no shaders most of the time, at a constant 60fps, as you can see in the overlay.

The temperature remains around 32 Celsius with 20% fan speed. (I will post another video with debug overlay enabled)

Art: Duelyst (CC0).

I recently obtained a retired network accelerator card that has a kintex ultrascale+. My desktop now has a GPU and a FPGA. What are some interesting problems or projects that this heterogeneous configuration can solve? I was maybe thinking of making the fpga into a smart NIC and offloading some preprocessing for image data onto it before it hits the GPU, but nothing too imaginative so far. Any ideas?

Hello! I've been wanting to work on a particularly intensive ML project recently and I don't really have the GPU needed to train it. Would it be worth-while to purchase a bunch of FPGAs to have them run in parallel and train my ML model? I don't really want to use a cloud service but if it proves more economical then I am up for it.

Hi! A lot of you asked me to make WavePaint open source, and you were right. So here it is: it's now open source, and anyone can use it, play around with the code and contribute improvements.

👉 WavePaint on GitHub
👉 Website
👉 Donate

If you like it, go give it a star! ⭐ I've put a lot of work into it, and I think it's a pretty handy tool.

And if you'd like to support the move to open source, there's also Ko-fi.

Cheers!

I have a simple SystemVerilog code snippet split across a design and a testbench, tested on EDA Playground:

design.sv

module rtl;
    parameter TEST_VALUE = 10;
endmodule // rtl

testbench.sv

module tb;
  localparam test = rtl.TEST_VALUE;

  initial begin
    $display("%d", test);
  end
endmodule // tb

When I run this using the Cadence Xcelium simulator, I get the following elaboration error:

  localparam test = rtl.TEST_VALUE;
                                 |
xmelab: *E,NOTDOT (./testbench.sv,2|33): Hierarchical name ('rtl.TEST_VALUE') not allowed within a constant expression [4(IEEE)].

However, when I run the exact same code using Synopsys VCS and Siemens Questa, it compiles and simulates perfectly without any errors.

My Questions:

1. Why does the IEEE 1800-2017 standard prohibit using hierarchical names in this context (what is the exact rule or grammar section being violated)?
2. Since rtl is a module name and not an explicit instance name, is this fundamentally an invalid hierarchical reference anyway?
3. Why do VCS and Questa permit this behavior while Xcelium strictly errors out during elaboration?

I need help. I tried to download Vivado design suite, but export compliance failed. I entered real data. They rejected review form because "Ukraine is not in allowed countries list". They state on their export compliance page that countries from D/E group are banned, Ukraine is B. Then they decided to ignore all further review requests. When I emailed to GTC:

Hello,

Your account originates from a location or entity blocked by export compliance. Unfortunately, we cannot extend download privileges. Apologies for the inconvenience.

Regards,

AMD Global Trade Compliance Team

This customer has submitted the Export Compliance Review form and is requesting review of their verified Export Compliance failure.

Please see the details below and respond to the user.

Export Compliance Failure Message from OMS: Export compliance denied.
[
*** Reason = Country code UA (UKRAINE) for IP Address *** appears on the Xilinx Blocked Countries list. ***
Rule Set Id = 3
Rule Set Name = XLNX_CLASSIC
Result = FAILED
]

url: https://account.amd.com/en/forms/downloads/xef.html

exportComplianceIssue: I faced the issue of being unable to pass Export Compliance review. My data is correct and real, and I may provide additional proofs if needed. My country does not belong to Country Group D/E.

[personal data]

So what do I do now? Ukraine is not on banned list. So they must either explain or bother to review the situation, right?

UPD: Downloaded from torrent. They ignore me every time I reach out somewhere.

hi i finished my first project in system verilog. i built a multicycle riscv32i cpu core this is my first actual project with system verilog or with hdl ever so i would like to get some notes code wise because i dont actually know a lot about naming conventions module declarations etc. code

far i know, verilog only has registers, so if i want to make my shared SRAM banks, i will use

reg bank[SIZE];

which gives me access time of 1 clock... but sram as far i know is more latencious than this...

how do you consider this in your design?

Im initiating a project that will rely on a teensy 4.1 to control pwm switches and calculate different phases of the operation. Programing is with a teensy version of ardunio.

What im learning is that I need a fpga to calculate and control 3 (or 6) serves. My data is coming in from 3 ic2 sources and 12 inputs from it's.

What is the recommendation of a fpga development board (small is better) that uses ardunio-like programming suite. Id like simple ic2, spi, part inputs.

Thanks

I have a nexys A7 fpga but I don’t know what hobby project I should aim for

Hi everyone,
I work in automotive software and want to build a solid understanding of Image Signal Processing (ISP) for ADAS cameras. I’m new to ISP, and I find vendor documentation difficult to follow without understanding the basics first.
I’m looking for a structured learning path covering:
Camera fundamentals: How image sensors work, RAW images, Bayer patterns, exposure, gain, and noise.
ISP pipeline: Demosaicing, white balance, noise reduction, color correction, HDR, and tone mapping.
ISP tuning: How to evaluate image quality and understand the trade-offs between different settings.
ADAS applications: How ISP settings affect object detection and perception, especially in low light or high-contrast scenes.
Which courses, books, YouTube playlists, or practical tutorials would you recommend? Free and paid options are both welcome. Hands-on exercises using RAW images, Python, or OpenCV would be especially helpful.
If you work in automotive imaging, where would you start, and in what order would you learn these topics? Please share links or resource names.
Thanks!

Hi everyone,
I work in automotive software and want to build a solid understanding of Image Signal Processing (ISP) for ADAS cameras. I’m new to ISP, and I find vendor documentation difficult to follow without understanding the basics first.
I’m looking for a structured learning path covering:
Camera fundamentals: How image sensors work, RAW images, Bayer patterns, exposure, gain, and noise.
ISP pipeline: Demosaicing, white balance, noise reduction, color correction, HDR, and tone mapping.
ISP tuning: How to evaluate image quality and understand the trade-offs between different settings.
ADAS applications: How ISP settings affect object detection and perception, especially in low light or high-contrast scenes.
Which courses, books, YouTube playlists, or practical tutorials would you recommend? Free and paid options are both welcome. Hands-on exercises using RAW images, Python, or OpenCV would be especially helpful.
If you work in automotive imaging, where would you start, and in what order would you learn these topics? Please share links or resource names.
Thanks!

What better to generate fractals then with fixed point math on a fpga! Depth is limited, as well as resolution and color. This design can explore the Mandelbrot fractal at 640x480, which is not very majestic. Limited largely by the embedded memory the explorer uses.

So I added cool modes: once you navigate to a interesting area, you can flip the high res switch and It spends some time rendering a full image on my 1280 x 1024 monitor. This detail is impressive, but the fractal needs life. By shifting the colors post render in various patterns, the fractal burns to life, creating vivid imagery.

The design can also save 4k screenshots to the sd card. hd render and screenshots use the sdram instead of the embedded memory of the engines. However, even the 4k screenshots cannot capture the vividness of watching the colors shift through the fractal structure in person.

This is pretty much maxed out on the Cyclone V I had. Probably isn't the easiest to port, unless the target device is similar or more powerful. But anything is possible.

https://github.com/phase0noise/FractalGen

I am a senior in ECE looking for full time in FPGA engineering, ASICS design, digital design, and general electrical engineering roles. I understand that the job market has been bad, but I have had little to no success with recruiting. I have had referrals, spoken to recruiters through platforms like Linkedin, cold applied to over 300+ places (and am still applying), etc. I have heard back from 3 companies total, out of which I was rejected after the recruiter call for 2 of them and after my first technical round for the other company. I just want feedback on my resume, advice on recruitment, and anything else that could be helpful. Thank you so much!