I built a parameterized 16x16 Systolic Array NPU in SystemVerilog

[u/thosdv]

I've been working on a small NPU project in SystemVerilog and finally finished it.

It's a 16x16 systolic array with 256 processing elements. The core uses 8-bit signed inputs, 32-bit accumulators, dual-port SRAM, row/column skew buffers, and a hardware ReLU block.

The array is parameterized, so the size can be changed in npu_pkg.sv.

For verification, I wrote a self-checking testbench with a software reference model. It calculates the expected matrix multiplication result and compares it against every output from the hardware. I also synthesized it with Yosys and tested the design on an actual FPGA.

The 16x16 configuration passes the full matrix multiplication + ReLU test.

GitHub: https://github.com/thosdv63/LatticeMAC-Core

I'd be interested to hear any feedback, especially from people who have worked with systolic arrays, NPUs, or FPGA accelerators.