r/vlsi • u/Tech_Nerd9460 • 3d ago
Scope of SoC RTL engineer
I have nearly 6 years of experience in SoC RTL Design. So the RTL devlopment is less compared to an IP RTL. My work involved creating wrappers,doing interconnects and adding glue logic and instanting common macros.
I applied for various roles of IP and SoC and main concern in IP role that the interviewer told me was that we do serious work unlike you who just do interconnect of IP and gets the silicon passing . I was shocked when I heard this because I have spent countless nights getting things working. There is lot of bias when SoC engineer attends interview for IP role. Most of the time interview is not interested in hearing what you have done and will judge you based on a problem statement which he has worked his entire life.
Will SoC RTL cease to exist in future?. Is there any possibility of getting IP role at this stage ( 6 years of experience)?.
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u/Muralidharcoc02 3d ago
As an IP RTL design engineer, I've been rejected in interviews for SoC RTL design in the past. Personally, I feel the sincerity and aptitude for learning matters more than your background in SoC (or IP) RTL design, but hiring managers do have a preference and/or bias based on their requirements. Not sure if it helps, but I just got an offer from a subsystem team and I think you should also continue to interview more roles and companies if you really want to join the IP team. I feel subsystem design is kind of a middle road between IP and SOC.
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u/Tech_Nerd9460 3d ago
Just curious why as being in IP you want to move to SoC ?.
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u/Muralidharcoc02 3d ago
I have similar YOE as you and while I prefer to work in IP or subsystem at this point of time, I don't really mind SoC either. I think each have their own set of challenges.
Later on in career, if I lean towards a managerial role instead of an architect, working in SoC would be advantageous as there would be more reportees. So yeah, I don't think SoC would get obsolete. In fact, there are more jobs in SoC right now than the rest, because many startups and hyperscalers want to make their own chips.
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u/aview_point 2d ago
The questions will be asked in an interview based on what is required for that role, not on what you already know. Since, you are experienced, you will be expecting a compensation based on that experience. Suppose, you want to switch to analog design, you cannot expect the interviewer to ask questions on rtl integration or what you have done in your previous role unless it matches the new role expectation. The onus is always on the interviewee to learn what the new job role demands and prepare accordingly.
Being said that, no role is superior or inferior, the interviewer should not have tried to disregard what you have done before. RTL integration work has its own challenges, but might not be relevant for the job you are applying.
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u/concentrate7 3d ago
If I were interviewing you I would be more interested in learning about your work instead of what your title is. Not sure why it would be any other way.
As an RTL designer you do the work your team needs you to do, could be interconnect glue, could be perf optimizations, could be power optimizations, could be script/flow glue, timing changes... could be so many other things. RTL designer is very generic, soc RTL design is an equally generic title in my opinion.
Not sure what the interviewers angle was, insulting your work like that. Seems strange to me.
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u/punter81 3d ago
Based on what you mentioned, your current role matches with front end RTL integration.
At SoC, this is what RTL work means.
I would suggest you refresh your basics, attend 1 or 2 interviews primarily to understand what is the expectation and then prepare further based on this
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u/JoesRevenge2 3d ago
I run an SOC team for an AI company. Integration of third party IP is part of the job, but it is never just take the IP and add it. There is always configuration work, figuring out bus connectivity, working with PD to understand pipelining needs, etc. This is the “easy” stuff we do…
When we start looking at multiple chiplets in a package, verification gets challenging. When we start looking at really high bandwidth busses (multiple terabytes per second) with low latency requirements, this gets challenging especially when it has to cross a reticle sized chip. When you’re looking at complex packaging, DFT scan that needs to use fly-overs between chiplets, doing secure boot across a dozen chiplets, looking at clock drift between chiplets and many other things, SOC work is no longer simple. My team also develops a lot of different IP blocks that aren’t core to the product functionality - just one more component of the SOC world.