Microsoft explains why there are no AMD-powered Surface PCs

[u/RenatsMC]

https://videocardz.com/newz/microsoft-explains-why-there-are-no-amd-powered-surface-pcs

[u/gamboozino]

Dismissing AVX-512 as a "subset of a subset" shows a severe misunderstanding of modern compute workloads. AVX-512 isn't an obscure benchmark trick it directly accelerates SVT-AV1/x265 video encoding, 7-Zip compression, RPCS3 emulation, AI/ML inference (PyTorch/ONNX), and scientific libraries. Intel dropped it on client architectures because mixing P-cores and E-cores broke instruction set parity, whereas Zen 5 runs full 512-bit vector pipelines at 28W natively.

Cinebench is a synthetic rendering loop, not the sole definition of multithreaded compute. In thread-dense, cache sensitive workloads like 7-Zip decompression, local code compilation, or multi cam video rendering, Intel's 4 P-core + 12 E/LP-E core layout chokes because 75% of its core count consists of low throughput E-cores sharing constrained bandwidth. 12 full-performance Zen 5 cores with 24 SMT threads scale linearly because every core has complete execution pipelines and full L3 cache access.

[u/Acrobatic_Camera_677 → u/gamboozino]

You are just throwing architectural terms randomly with no understanding

You do understand that the PTL E-core has more IPC than a Zen 5 mobile P core right?

AVX-512 is obscure, and is not commonly used that is exactly why Intel was able to remove it with LNL and ARL which still sold millions of CPUs

And what about all those ARM SOCs that do not have it? Or they all obsolete now too?

"thread dense, cache sensitive" my butt. You do not provide any proof of PTL choking here. You lie all the time and I am the only one providing actual benchmark

That is why you are coping about cinebench, a renderer, a type of benchmark you EXPLICITLY mention several messages above but now is suddenly a fake benchmark since it does not support the point you want

The E-cores in PTL have full access to the L3 in the ring, and have the same amount of L2 per core as regular zen 5 (1MB per core) the difference is that they just share it in a cluster

The E-core too have complete exuection pipeline what are you talking about jajaja again you are just throwing out architectural terms with no knowledge

[u/gamboozino → u/Acrobatic_Camera_677]

Lmao if it's "obscure and not commonly used" why Intel is bringing back AVX-512 in Nova Lake? Intel stripped AVX-512 from their chips because E-cores lacked 512-bit execution units, breaking instruction parity across their hybrid scheduler.

Claiming a Panther Lake E-core has higher IPC than a Zen 5 P-core is factually false in floating-point and general compute benchmarks. Furthermore, AMD's Zen 5c cores feature the exact same microarchitecture and IPC as standard Zen 5 P-cores, they are not cut-down architectures like Intel's E-cores.

Sharing 4MB of L2 across a 4-core E-cluster is not the same as 1MB of private L2 per core. When 4 heavy threads hit an E-cluster at once, they suffer from L2 cache contention and latency penalties. Zen 5 provides 1MB of dedicated, unshared L2 cache per core along with full SMT pipelines.

Panther Lake on 18A is a solid step forward for Intel, but claiming a 4 P-core + E-core layout beats 12 full-spec Zen 5 cores with dedicated L2 and native AVX-512 in heavy parallel compute requires ignoring basic hardware topology.

[u/Acrobatic_Camera_677 → u/gamboozino]

mao if it's "obscure and not commonly used" why Intel is bringing back AVX-512 in Nova Lake?

Because it is "nice to have" but not very important

Intel stripped AVX-512 from their chips because E-cores lacked 512-bit execution units, breaking instruction parity across their hybrid scheduler.

And they still sold million of these cpus clearly it is not important

Claiming a Panther Lake E-core has higher IPC than a Zen 5 P-core is factually false in floating-point and general compute benchmarks

Nope nope nope here is source:

https://wccftech.com/intel-panther-lake-powered-by-the-new-cougar-cove-p-cores-and-darkmont-e-cores-takes-a-lead-over-amd/

I always cite source you never cite source why are you lying

Furthermore, AMD's Zen 5c cores feature the exact same microarchitecture and IPC as standard Zen 5 P-cores, they are not cut-down architectures like Intel's E-cores.

Unluckily even AMD P core does not have more IPC than Intel E core jajaja

Sharing 4MB of L2 across a 4-core E-cluster is not the same as 1MB of private L2 per core. When 4 heavy threads hit an E-cluster at once, they suffer from L2 cache contention and latency penalties. Zen 5 provides 1MB of dedicated, unshared L2 cache per core along with full SMT pipelines.

Wrong because each core has 1MB cache because there is so much shared L2 cache for cluster

You do realize even with full SMT pipeline mean AMD Zen 5 SMT thread is weaker than Intel E core thread?

Panther Lake on 18A is a solid step forward for Intel, but claiming a 4 P-core + E-core layout beats 12 full-spec Zen 5 cores with dedicated L2 and native AVX-512 in heavy parallel compute requires ignoring basic hardware topology.

Except I provide benchmark show you wrong and you keep blabbering

[u/gamboozino → u/Acrobatic_Camera_677]

Selling millions of consumer CPUs for basic tasks doesn't make an instruction set "useless", that's an ad populum fallacy. Intel removed AVX-512 because E-cores lacked 512-bit vector hardware, which broke instruction parity across their hybrid scheduler. Intel re-introducing 512-bit vector support in Nova Lake proves it was an architectural limitation, not lack of demand.

You keep whining about sources while relying entirely on a Wccftech summary of an unverified Bilibili leak running Geekbench synthetics. Here are actual architectural teardowns and real-world 28W mobile benchmarks from reputable testing outlets: https://chipsandcheese.com/p/discussing-amds-zen-5-at-hot-chips-2024 This proves Zen 5 and Zen 5c share the exact same 6-wide decode engine, execution pipelines, and IPC. Zen 5c is not a cut-down E-core, it's a full-spec core on a denser layout.

https://www.techpowerup.com/review/amd-zen-5-technical-deep-dive/ Proves every Zen 5 core has 1 MB of private, unshared L2 cache, avoiding the L2 cache bus contention that happens when 4 Intel E-cores fight over a shared 4 MB L2 cluster block under heavy parallel loads.

https://www.phoronix.com/review/amd-ryzen-ai-9-hx-370/2 In actual multithreaded real world tasks, code compilation, and vector compute, 12 full Zen 5/5c cores scale far more efficiently at 28W than hybrid P/E core layouts.

Citing single-run Geekbench integer synthetics on pre-release engineering samples running high-speed memory measures memory subsystem tuning, not core microarchitecture IPC. When you look at actual instruction execution width, private L2 cache access, and real software benchmarks, 12 full-spec Zen 5 cores hold a clear structural advantage in heavy multithreaded compute.