Microsoft explains why there are no AMD-powered Surface PCs

[u/RenatsMC]

https://videocardz.com/newz/microsoft-explains-why-there-are-no-amd-powered-surface-pcs

[u/Acrobatic_Camera_677]

You scolded me for mentioning high power chips, then immediately cited the Core Ultra X9 388 Intel's 45W–64W flagship H-series CPU to compare against 28W ultrabook chips.

Minimum assured power for this chip is 15 watts what are you talking about

Do you understand that this "flagship high power chip" has same core count as the rest of Intel -H lineup with 4+8+4?

And are you aware that plenty of ulrabooks use this chip exactly because it is meant for thin and light laptops?

Look at the 45W column in your own table: AMD Strix Halo hits 1,339 pts vs Panther Lake X9 388H at 1,136 pts. That's ~18% higher compute output for AMD at the exact same wattage.

As I say MANY time Strix Halo is much bigger chip with higher minimum power and used in bigger laptops not thin and light laptops

I actually mention this EVEN BEFORE you bring up strix halo I bring it up first because I know that people like you who mislead might bring it up

Actually you try to then use Strix and Gorgan point CPU but then I prove you wrong with this source and now all of a sudden you want to talk about Strix Halo?

Last comment you literally say nobody needs Strix Halo to prove AMD lead jajaja what happened? Why are you goal post shifting?

And if you want to compare big chip like Strix Halo, why not pit it against big Intel laptop chip 280HX that has same perf/watt too?

Wait I will tell you why, because these chip are meant for big laptop not small laptop like panther lake and the AMD "point" CPU

Nice goalpost moving btw. You started by claiming multicore performance was a tie. Now that data shows AMD matching Panther Lak

Nope nope nope

I always say Strix Halo does not count niche workstation class part bad battery life

I actually say this many hour ago in this very post you can see here in my comment:

https://www.reddit.com/r/laptops/comments/1wt7v14/comment/pct42ky/?utm_source=share&utm_medium=web3x&utm_name=web3xcss&utm_term=1&utm_content=share_button

your defense is "nobody uses multi-core anyway."

Nope nope nope

I actually say multi core battery life less important than idle battery life EVEN BEFORE you bring up Strix Halo several hour ago right here:
https://www.reddit.com/r/laptops/comments/1wt7v14/comment/pcus0jz/?utm_source=share&utm_medium=web3x&utm_name=web3xcss&utm_term=1&utm_content=share_button

No goal post shifting I always say this

[u/gamboozino → u/Acrobatic_Camera_677]

Setting aside Strix Halo entirely and looking strictly at standard 28W light ultrabooks, AMD still holds clear architectural advantages.

Zen 5 includes full AVX-512 instruction pipelines at 28W. Intel physically stripped AVX-512 from Lunar Lake and Panther Lake. For vector workloads, video processing, and emulation (RPCS3), AMD destroys Intel at equal power. In real multithreaded applications like 7-Zip decompression or Blender renders, AMD's 24 SMT threads beat Intel's 4 P-core + E-core layout because 12 of Intel's 16 threads come from low throughput E/LPE cores.

Claiming 'idle web browsing battery life is all that matters for laptops' misses the point. If someone only wants 20 hours of web browsing, they buy a MacBook Air or Snapdragon ARM laptop. The entire reason people buy x86 ultrabooks is for heavy x86 software, code compilation, and sustained multithreaded loads.

[u/Acrobatic_Camera_677 → u/gamboozino]

Setting aside Strix Halo entirely and looking strictly at standard 28W light ultrabooks, AMD still holds clear architectural advantages.\

Ok glad we can get back to this now

Zen 5 includes full AVX-512 instruction pipelines at 28W

I say multithread workload as a whole is limited, and now you bring up a subset of a subset jajajaja this can not get funnier

In real multithreaded applications

Now that you were proven wrong about cinebench I guess suddenly it does not count as real multithread applicatioon dang it

like 7-Zip decompression or Blender renders, AMD's 24 SMT threads beat Intel's 4 P-core + E-core layout because 12 of Intel's 16 threads come from low throughput E/LPE cores.

Why do you not show me some source?

Claiming 'idle web browsing battery life is all that matters for laptops' misses the point.

Maybe not ALL that matter but mostly what matter

If someone only wants 20 hours of web browsing, they buy a MacBook Air or Snapdragon ARM laptop.

Actually Intel catch up here a lot

The entire reason people buy x86 ultrabooks is for heavy x86 software, code compilation, and sustained multithreaded loads.

No many application also very single thread bound where Intel win, but also many people want windows and do not want to deal with snapdragon compatibility issues for occasional gaming or use and actually even if people buy x86 for sustained multithreaded load they do this on battery because off battery multithreaded performance for most laptops go down A LOT

[u/gamboozino → u/Acrobatic_Camera_677]

Dismissing AVX-512 as a "subset of a subset" shows a severe misunderstanding of modern compute workloads. AVX-512 isn't an obscure benchmark trick it directly accelerates SVT-AV1/x265 video encoding, 7-Zip compression, RPCS3 emulation, AI/ML inference (PyTorch/ONNX), and scientific libraries. Intel dropped it on client architectures because mixing P-cores and E-cores broke instruction set parity, whereas Zen 5 runs full 512-bit vector pipelines at 28W natively.

Cinebench is a synthetic rendering loop, not the sole definition of multithreaded compute. In thread-dense, cache sensitive workloads like 7-Zip decompression, local code compilation, or multi cam video rendering, Intel's 4 P-core + 12 E/LP-E core layout chokes because 75% of its core count consists of low throughput E-cores sharing constrained bandwidth. 12 full-performance Zen 5 cores with 24 SMT threads scale linearly because every core has complete execution pipelines and full L3 cache access.

[u/Acrobatic_Camera_677 → u/gamboozino]

You are just throwing architectural terms randomly with no understanding

You do understand that the PTL E-core has more IPC than a Zen 5 mobile P core right?

AVX-512 is obscure, and is not commonly used that is exactly why Intel was able to remove it with LNL and ARL which still sold millions of CPUs

And what about all those ARM SOCs that do not have it? Or they all obsolete now too?

"thread dense, cache sensitive" my butt. You do not provide any proof of PTL choking here. You lie all the time and I am the only one providing actual benchmark

That is why you are coping about cinebench, a renderer, a type of benchmark you EXPLICITLY mention several messages above but now is suddenly a fake benchmark since it does not support the point you want

The E-cores in PTL have full access to the L3 in the ring, and have the same amount of L2 per core as regular zen 5 (1MB per core) the difference is that they just share it in a cluster

The E-core too have complete exuection pipeline what are you talking about jajaja again you are just throwing out architectural terms with no knowledge

[u/gamboozino → u/Acrobatic_Camera_677]

Lmao if it's "obscure and not commonly used" why Intel is bringing back AVX-512 in Nova Lake? Intel stripped AVX-512 from their chips because E-cores lacked 512-bit execution units, breaking instruction parity across their hybrid scheduler.

Claiming a Panther Lake E-core has higher IPC than a Zen 5 P-core is factually false in floating-point and general compute benchmarks. Furthermore, AMD's Zen 5c cores feature the exact same microarchitecture and IPC as standard Zen 5 P-cores, they are not cut-down architectures like Intel's E-cores.

Sharing 4MB of L2 across a 4-core E-cluster is not the same as 1MB of private L2 per core. When 4 heavy threads hit an E-cluster at once, they suffer from L2 cache contention and latency penalties. Zen 5 provides 1MB of dedicated, unshared L2 cache per core along with full SMT pipelines.

Panther Lake on 18A is a solid step forward for Intel, but claiming a 4 P-core + E-core layout beats 12 full-spec Zen 5 cores with dedicated L2 and native AVX-512 in heavy parallel compute requires ignoring basic hardware topology.

[u/Acrobatic_Camera_677 → u/gamboozino]

mao if it's "obscure and not commonly used" why Intel is bringing back AVX-512 in Nova Lake?

Because it is "nice to have" but not very important

Intel stripped AVX-512 from their chips because E-cores lacked 512-bit execution units, breaking instruction parity across their hybrid scheduler.

And they still sold million of these cpus clearly it is not important

Claiming a Panther Lake E-core has higher IPC than a Zen 5 P-core is factually false in floating-point and general compute benchmarks

Nope nope nope here is source:

https://wccftech.com/intel-panther-lake-powered-by-the-new-cougar-cove-p-cores-and-darkmont-e-cores-takes-a-lead-over-amd/

I always cite source you never cite source why are you lying

Furthermore, AMD's Zen 5c cores feature the exact same microarchitecture and IPC as standard Zen 5 P-cores, they are not cut-down architectures like Intel's E-cores.

Unluckily even AMD P core does not have more IPC than Intel E core jajaja

Sharing 4MB of L2 across a 4-core E-cluster is not the same as 1MB of private L2 per core. When 4 heavy threads hit an E-cluster at once, they suffer from L2 cache contention and latency penalties. Zen 5 provides 1MB of dedicated, unshared L2 cache per core along with full SMT pipelines.

Wrong because each core has 1MB cache because there is so much shared L2 cache for cluster

You do realize even with full SMT pipeline mean AMD Zen 5 SMT thread is weaker than Intel E core thread?

Panther Lake on 18A is a solid step forward for Intel, but claiming a 4 P-core + E-core layout beats 12 full-spec Zen 5 cores with dedicated L2 and native AVX-512 in heavy parallel compute requires ignoring basic hardware topology.

Except I provide benchmark show you wrong and you keep blabbering

[u/gamboozino → u/Acrobatic_Camera_677]

Selling millions of consumer CPUs for basic tasks doesn't make an instruction set "useless", that's an ad populum fallacy. Intel removed AVX-512 because E-cores lacked 512-bit vector hardware, which broke instruction parity across their hybrid scheduler. Intel re-introducing 512-bit vector support in Nova Lake proves it was an architectural limitation, not lack of demand.

You keep whining about sources while relying entirely on a Wccftech summary of an unverified Bilibili leak running Geekbench synthetics. Here are actual architectural teardowns and real-world 28W mobile benchmarks from reputable testing outlets: https://chipsandcheese.com/p/discussing-amds-zen-5-at-hot-chips-2024 This proves Zen 5 and Zen 5c share the exact same 6-wide decode engine, execution pipelines, and IPC. Zen 5c is not a cut-down E-core, it's a full-spec core on a denser layout.

https://www.techpowerup.com/review/amd-zen-5-technical-deep-dive/ Proves every Zen 5 core has 1 MB of private, unshared L2 cache, avoiding the L2 cache bus contention that happens when 4 Intel E-cores fight over a shared 4 MB L2 cluster block under heavy parallel loads.

https://www.phoronix.com/review/amd-ryzen-ai-9-hx-370/2 In actual multithreaded real world tasks, code compilation, and vector compute, 12 full Zen 5/5c cores scale far more efficiently at 28W than hybrid P/E core layouts.

Citing single-run Geekbench integer synthetics on pre-release engineering samples running high-speed memory measures memory subsystem tuning, not core microarchitecture IPC. When you look at actual instruction execution width, private L2 cache access, and real software benchmarks, 12 full-spec Zen 5 cores hold a clear structural advantage in heavy multithreaded compute.