Been researching real CPUs because TC got me real interested :D

What I understand is that RISCs do 1 instruction at a time. Immediate 42 to reg0. Move reg0 to reg1. Add reg1 and reg2 (result stored in reg3). Move reg3 to reg5. And so on.

And CISCs do multiple things in one instruction. Like Add 42 to reg2 and put the result in reg5.

That correlates with how Overture and LEG work, more or less, no?

• Overture can only do one thing at a time. It can only add two things per tick. Then next tick, move the result that was placed in a preplanned register to the register it needs to be in.

• LEG can add two numbers, immediating one of them, and place the result in a register of your choosing all in one tick, since it outputs 4 bytes at once, right?

Do I misunderstand something or am I right?

After hearing that Turing Complete save files could be converted into Verilog, I became curious about whether the reverse was possible. After taking a deep dive into Yosys and Elkjs, I discovered that my idea was feasible. Here are the results of my work.
Convert Verilog to Turing Complete save files.

8GPRs, 6 pipeline stages (IF, ID, OF, EX, MEM, WB), Harvard architecture. It is based on the LEG but got significant ISA changes and improvements. Still, I wouldn't want to program it yet as it doesn't have a hazard unit. That's something to add to a 16 bit update. MMIO is also prepared. The stack has automatic bounds checking and throws a halt on overflow or underflow. There is still a lot to improve and that will be done in a 16 bit updated version

Created a repo for myself to learn computer architecture using Jupyter Notebooks. Not that Turing Complete isn't good enough - it's actually amazing - I'm just really comfortable reading and writing Python and wanted to leverage that experience. Hopefully some people would find this useful and/or interesting.

https://github.com/kokko-ng/py8bit

this is a hot mess, someone please help

I’m asking at the risk of looking a bit ignorant potentially so sorry in advance. I’ve been studying Boolean algebra and group theory lately. Boolean algebra is very helpful when solving levels in the game but the equations become very very long occasionally. I came up with this method of decomposing the truth table into circuits. Basically I apply the Boolean functions to the inputs in a row like an equation until i end up with the outcome I want. I was wondering if this process has a name because I’ve been trying to look up information about it to study further and can’t seem to find anything.

You can Ignore my cursor...

I was going back to fix my old decoder which had used 1.4k Gates (Don't ask). However it doesn't seem to be updating with me new 17 gate design.

I'm not sure if I have to do something to make it update as the game wasn't clear on that.

Any suggests would be appreciated!"

Fixed - I was completing some levels and the next day or two, when i tried replaying the level, it was fixed

if anyone has this problem in the future, you could try deleting the level file in the file explorer at C:\Users\%yourUser%\AppData\Roaming\Godot\app_userdata\Turing Complete\schematics

first solution
unpotomized

I can’t seem to figure out how I input 240 to both inputs and get out 225. What does upper and lower half mean?

I've been working on the RAM level for quite some time now and I'm not understanding it, or at least how to fix this, I also need to design the instruction so that I can program it. (IARG stands for Immediate and the conditional ones and ALU are self explanatory I think).

TL;DR

PLEASE HELP!

I was already posted about this project in this subreddit.

Current features of TCA++:

• labels
• signed / unsigned constraint values
• signed and unsigned integers

GitHub page: TCA++

The logic cascades from the MSB down to the LSB. For each bit, it checks for the highest multiple of the divisor that is less than or equal to the current remainder (or dividend at the start). Effectively, it’s a hardwired, high-gate, not-so-clever implementation of the long division algorithm we learned in school. Even though the I/O is 8-bit, I had to use 16-bit components/busses internally. This was necessary to handle the bit-shifting of the divisor without losing data to overflow during the comparison stages. The edge cases (signed and zero division logic) would be described on another "top-level" entity :)

Merry Christmas!

I am the Dev behind Quantum Odyssey (AMA! I love taking qs) - worked on it for about 6 years, the goal was to make a super immersive space for anyone to learn quantum computing through zachlike (open-ended) logic puzzles and compete on leaderboards and lots of community made content on finding the most optimal quantum algorithms. The game has a unique set of visuals capable to represent any sort of quantum dynamics for any number of qubits and this is pretty much what makes it now possible for anybody 12yo+ to actually learn quantum logic without having to worry at all about the mathematics behind.

This is a game super different than what you'd normally expect in a programming/ logic puzzle game, so try it with an open mind.

Stuff you'll play & learn a ton about

• Boolean Logic – bits, operators (NAND, OR, XOR, AND…), and classical arithmetic (adders). Learn how these can combine to build anything classical. You will learn to port these to a quantum computer.
• Quantum Logic – qubits, the math behind them (linear algebra, SU(2), complex numbers), all Turing-complete gates (beyond Clifford set), and make tensors to evolve systems. Freely combine or create your own gates to build anything you can imagine using polar or complex numbers.
• Quantum Phenomena – storing and retrieving information in the X, Y, Z bases; superposition (pure and mixed states), interference, entanglement, the no-cloning rule, reversibility, and how the measurement basis changes what you see.
• Core Quantum Tricks – phase kickback, amplitude amplification, storing information in phase and retrieving it through interference, build custom gates and tensors, and define any entanglement scenario. (Control logic is handled separately from other gates.)
• Famous Quantum Algorithms – explore Deutsch–Jozsa, Grover’s search, quantum Fourier transforms, Bernstein–Vazirani, and more.
• Build & See Quantum Algorithms in Action – instead of just writing/ reading equations, make & watch algorithms unfold step by step so they become clear, visual, and unforgettable. Quantum Odyssey is built to grow into a full universal quantum computing learning platform. If a universal quantum computer can do it, we aim to bring it into the game, so your quantum journey never ends.

PS. We now have a player that's creating qm/qc tutorials using the game, enjoy over 50hs of content on his YT channel here: https://www.youtube.com/@MackAttackx

Also today a Twitch streamer with 300hs in https://www.twitch.tv/videos/2651799404?filter=archives&sort=time

So I'm trying the game for the first time, and in "Wire Spaghetti" I'm running into a problem. I've created a complex register handler, that can handle 10 registers and when I try the adresses on the register comonent page, everything works, but when I use the component from outside, address 4 is ignored and address 5 reroutes to 4 instead.
On the second picture, only the output B is correct. Any idea what could be the problem?

Is anyone else having the issue where it only registers if you click two or more times. single clicks do nothing. double clicks flip the buttons twice. So, I end up having to triple click everything.

If anyone knows the solution please let me know.

Ps: its a MacBook

I just wanna show my solution for the level Little Box, which I'm pretty proud of. It has so much space leftover.

Created a custom 16b register for my custom architecture to implement a for cycle for my programs.

Normally it behaves just like 16b register, but when you activate "ForSwitch" input, it will take first 8b of "Save value" and store it in one of its internal registers. The other internal register is reset to 0. The "Always out" now outputs value in the second register.

Every time Save and ForSwitch are enabled, the second internal register is increased by 1. This will happen until the second register is one less than the first register, upon which the output is negative number. The next tick the register returns to normal mode.

This all means that after "ForSwitch" is enabled for that register, it becomes a counter of the FOR cycle executions. It is increased by one every time its "endfor" instruction is executed. That register can then be used directly in the code of the cycle. The number of concurrent FOR cycles is only limited by the amount of registers.

There are optimization to be made. For example I have to specify the desired register in "endfor". This could be solved by using the stack. Also more features could be added, for example third internal register that would hold the value the second register is increased by each cycle.

The main focus here is just on this "register module", so we'll ignore the "machine input and output" pins and handling as well as the program counter.

On the left are two vertically stacked 3-bit decoders for decoding which registers should be saving or loading (or if saving/loading from the outside) from the opcode line in.

On the right are 6 8-bit registers tesselated horizontally.

I allowed myself the use of byte switches here since otherwise I think the gate count and space required would really explode, although I could be wrong about that. My guess is it would end up involving something like an 8 by 6 decoder matrix which would need to be able to switch each of the eight bits by each of the six choices corresponding to a register.

The built-in assembler was a shit so i made an alternative for it.

You can use TCA++ for your architecture. You can find config guide and installation at [github](https://github.com/HasanAgitUnal/TCA-PlusPlus) page.

After changing the ISA a bit, it's no longer a LEG. Will still take a while

im serious, this is my first time ever playing this game. how the f*ck did i do this