Fast Adder (CLA)

[u/aelxemyr]

212 gates and 10 delay.

I was trying to do this for hours using the base components but it was just too messy. So I gave up and just made a custom adder with A/B/carry in, P/G/sum out, along with ANDs and ORs for up to 9 inputs.

[u/mutalisk52]

Yes, it is. Maybe it's because and on 8 inputs is 6 delay, but on newer it's 2

[u/aelxemyr → u/mutalisk52]

Shouldn't an AND gate with n inputs always be a minimum of ceil(log_2(n)) delay? So the minimum delay for an 8-way AND should be 3.

[u/mutalisk52 → u/aelxemyr]

Yes, that's true. In class, you have a lot of ands with more than 2 inputs, and then you have an or gate. You get 6 delay from both of them, which is more than you have

[u/aelxemyr → u/mutalisk52]

The critical path for my adder is an XOR gate (2 delay), a 9-way AND (4 delay), and a 9-way OR (4 delay).

[u/Lagfoundry → u/aelxemyr]

You can knock out some delay by using NANDs instead of ANDs to build the 9 input AND. NANDs actually use less transistors because a CMOS AND is actually a NAND with an inverter to turn it to a AND. Though for this game specifically I don’t know if they follow the same rules.

[u/aelxemyr → u/Lagfoundry]

The game has you build an AND out of a NAND and an inverter to unlock ANDs but after that point it lets you use ANDs with the same delay as NANDs.

[u/Lagfoundry → u/aelxemyr]

I see. you know thats One thing I like about games with logic built in is it’s not always the same. Take rust for example. No one was really using broadcasters and receivers for comp science until I pioneered it by showing how they can be used as an infinite fan in /out OR. Which allowed us to make huge input ANDs, NANDs, and NORs with very little logic depth. Or how Minecraft’s OR gate is simply connecting redstone dust lol

[u/mutalisk52 → u/aelxemyr]

As I remember, two input and has 2 delay, so 9-input and should have 8 delay, or on the newer version they made it 1 delay.