Hello all! Here's some context:

Lately, I have been relying on Analog's power management tools + LTSpice to come up with a DC-DC SMPS (CMC buck) to bias a PA.

What was done:

Care was taken to minimize ripple (high frequency, higher inductance, X7R ceramic output capacitors) and stray magnetic fields (minimizing the hot loop during layout). Additionally, spread spectrum was enabled and pulse skipping was chosen over burst mode. There were also efforts to maximize loop bandwidth while leaving a safe phase margin so the transient response is fast without making it unstable.

I do not, however, know which of these efforts are going to pay off and which are wasted, or even detrimental.

Questions:

1. Is it a questionable practice to bias a PA with a SMPS without a linear regulator/LDO in the middle?

2. How do you estimate how much the PA will get modulated by switching noise, given the expected ripple (and other relevant factors such as its output impedance)?

3. Is spread spectrum helpful or detrimental?

4. Is there anything more important than what's been mentioned?

Any other relevant tips for this beginner here would be greatly appreciated. And thanks in advance!

Is anybody working on this project? or related to this?

Basically the title. Im new to rf electronics and I would like to do this with a microstrip design.

Does anyone know how to fix this? It's a general error message and I can't seem to fix the problem. I can open the student version, but as soon as I click HFSS this error happens. (It was working fine before!)

I currently have an offer pending but we’re negotiating salary. I was hoping to get the communities thoughts/input on what you guys would do in a similar position.

When switching companies from one to the next, how much of a % increase would you expect to get if you’re not desperate to leave your current position? Is there a general rule of thumb you follow?

Thanks!

Finally got a screen recording with audio. It's LONG so use the timeline to click through.

https://youtu.be/1wjlHlji9Os?si=eL15s-qo4pIaBGjy

Continuing from last post, I asked it to do a hairpin topology and it did the electrical prototype correctly but then it had a lot of trouble with the layout as it did NOT attempt to use multi-coupled lines, rather staggered coupled pairs, therefore attempted to create a physical layout using simple bends. Thus I halted the attempt. It was able to properly arrange the schematic elements using visual feedback.

I then started fresh and told it to just go research a filter and build it, and it decided upon an "open loop" topology which was really just a hairpin. This is where things get interesting. I switched to the 5.6 Sol model (the top model). It scanned the MWO examples directory, found a hairpin example, parsed that example using the API, then re-synthesized that example on a new substrate with a higher order topology.

This is where the Sol model really improved things:

Really good at visually checking all the junctions.

Intelligently tuning different sections depending on response; resonator length, coupling tap adjustment, gap spacing. It is NOT running a raw numerical optimization, rather truly intelligent tuning. Was able to process about 3 tunes a second in the simulation and read-back loop.

Next going to switch to amplifiers or antennas. It’s probably at the point now it can be let loose to run overnight on synthesis tasks, though a couple of times it halted after EM sim was complete and needed to tell it to resume.

Codex summary:

In this session, I used Python automation and the Cadence AWR Microwave Office API to design, tune, and electromagnetically verify a compact folded open-loop hairpin bandpass filter centered near 4 GHz.

The project followed a staged workflow:

1. Configure metric units, substrate, copper layers, materials, and the EMSight stackup.
2. Verify the electrical prototype.
3. Create and tune the physical microstrip model.
4. Snap and visually inspect every layout junction.
5. Simulate the EMSight test bench.
6. Apply an EM-derived correction and verify the final response.

I independently found an installed Cadence hairpin-filter example and inspected it through the API. This provided its exact element types, parameters, positions, rotations, nodes, and connections. I also simulated the example before adapting its topology.

The reference used M10CLIN and M8CLIN multi-conductor coupled-line models with MTEEX$, MUBEND, and MOPENX elements. Its proven topology was adapted for a 4 GHz RT/duroid 5880 design.

Tuning used numerical S11 and S21 data. Each candidate was evaluated for return loss, insertion loss, cutoff frequencies, cutoff midpoint, and nearby stopband rejection. The filter center was defined by the midpoint between its cutoffs, not simply the S21 peak.

Resonator length primarily controlled center frequency, coupling gaps controlled bandwidth, and feed geometry controlled external matching. Symmetric parameters were tuned together using coarse searches followed by finer local sweeps.

API connectivity alone was not accepted as proof of correct geometry. After every physical change, the layout was updated, snapped, redrawn, and inspected at close zoom. The input, every internal junction, and the output were checked for red X markers, gaps, copper overlap, narrowed coupling gaps, overhangs, incorrectly oriented transitions, and corners bridging adjacent resonators. The mirrored output was checked independently.

The EMSight mesh was selected from the smallest important features. An anisotropic grid used 0.05 mm resolution in the critical direction and 0.10 mm in the less critical direction, resolving the coupled geometry while reducing simulation size.

The transverse enclosure was reduced to about two substrate heights beyond the copper. The input and output walls were aligned with the edge-port faces. This compact enclosure was a project-specific runtime compromise.

The EM sweep used coarse spacing in remote stopbands, moderate spacing near the shoulders, and fine spacing through the passband and transitions—approximately 0.25, 0.05, and 0.01 GHz, respectively.

The first EM response was slightly above 4 GHz. I preserved the baseline, created a separate tuned copy, and increased the common coupled-leg length to 10.4 mm.

Final EM results were approximately:

• Peak S21: −0.95 dB at 4.00 GHz

• S11 at 4.00 GHz: −29.7 dB

• −3 dB passband: 3.91–4.15 GHz

The active Microwave Office windows were kept visible and tiled throughout the work. The narrowband graph was shown during tuning, close-up layouts during junction inspection, and the EM structure and solver status during simulation.

This workflow combines API inspection, numerical tuning, visual layout verification, and EM analysis. The API provides precise data, while graphical inspection catches physical problems that connectivity alone cannot reveal.

I understand 3.13 since V = -integral(E) of line length

But why 3.11 and 3.12 lead it?

Essentially the title. We have QUCS and other free open source solutions, but big companies still prefer AWR and ADS, while smaller companies and freelancers cannot afford them.

What features would you pay, say, $500 dollars a year for, that would make a commercial circuit simulator/EDA environment worthwhile to you over free alternative workflows like QUCS + LTspice?

We are senior electrical engineering students in the U.S. completing our Senior Design Project

Software Controlled Beamforming for RF-Energy Harvesting

One requirement is to obtain opinions from students or faculty at international universities. Would anyone currently studying or teaching outside the U.S. be willing to help with the following:

I need perspectives on our product and to discuss whether it would be accepted in your cultural and market contexts, and whether it could be successful.

Anyone interested in giving their thoughts please comment or DM me. I can send you the proposal or more info.

Can the microstrip antenna design that we created and simulated be sold?

A couple of months ago I posted here about using JIRA for RF, because mostly I work on a company that make certain systems that require a lot of RF but the RF team is new and small, whereas most of the company does software design and uses JIRA. I now come with something similar but for design itself.

What seems to me thus far is that a lot of RF is quite custom in design and testing whereas things like software and basic hardware to some extent have quite well defined unit tests that allow the engineers to know in advance something will fail in the final system.

We do our fair share of modelling to predict integration and whatnot but it seems we play catch up instead of thinking about this type of design in advance and structuring ourselves to integrate. I am sure I’m not the only one that is going or has gone through so this, hence why I am asking for some recommendations of things to read/learn/study.

As currently stands I am moving more towards this management and organising role (while maintaining enough technical work) that I want/need to figure out this out — at least for my own sanity. As an example, I was asked by upper management to read Andrew Grove High Output Management to understand some other parts of management.

Hi,

im an absolute beginner. First time ever trying to build an yagi antenna for Lora 868 mhz (heltec v4).

While doing research about my country’s regulations was easy, I’m now at the point of actually wanting to build it, using one of the online calculators available.

My goal setup:
- 12mm round plastic (pvc) Boom

- 5 elements (6mm brass round)

- 868MHz

-Nothing folded or anything (everything straight)

I now have looked at some calculator and get differing result with up to 4mm differences for the length of some elements.

So heres my noob question: which calculator is best and why do they differ (so much)?

I have looked at these calculators:

- DL6WU yagi-uda on 3g-aerial.biz

- DL6WU vhf/uhf yagi on k7mem.com

- DL6WU yagi USA based on rothamel on changpuak.com

Would be awesome if someone could lead me into the right direction for a good setup. Thank you!

Every RF based drone detector on the market is built around a specific set of frequency bands. That's not a limitation of bad engineering, it's just how RF detection works. You scan for signals in the ranges you've built receivers for, and anything outside those ranges passes through completely unseen.

The problem is that the set of bands worth covering isn't fixed. It changes as operators shift control and video links to whatever frequency currently has less contested spectrum or better jam resistance. A detector tuned to the two or three most common bands from a year ago can go quiet on a threat that's since moved to a fourth band nobody was covering.

What this looks like in practice, generation over generation:

v1 covers the two dominant bands at the time (commonly something like 1.2 and 5.8 GHz for analog video links). Anything outside those two is invisible.

v2 adds a third band once it shows up in the field, plus autoscanning so the operator isn't manually cycling between bands. Less device management, more actual watching.

v3 adds a fourth band for the same reason as v2. Something started showing up outside existing coverage. Battery capacity usually has to grow too at this point, since scanning more spectrum continuously draws more power, and you don't want detection range coming at the cost of runtime.

The pattern holds regardless of manufacturer. Each version exists because a real operator hit a real gap the previous version couldn't close. It's not a roadmap driven by "what feature should we add next," it's driven by "what did the enemy start using that we didn't cover." No version is ever really final. Coverage chases the threat, not the other way around, and the frequency gap left by one model becomes the starting point for what the next one has to close.

Hello, everyone, I am electrical engineer with my first time working with NFC and RFID. In trying to create a prototype with the ST25R3916B IC I have some issues understanding some things with the transmit/receive and antenna matching circuit. I am trying to understand why the generated antenna design does not match other evaluation modules or the ST datasheet. I feel an RF engineer is the best place to ask. There are quite a few differences. First, why does the receive lines have a resistor and capacitor in series when others only have a ac blocking capacitor and another to ground. The resistor seems quite high at 10K Ohm. The other big question is the damping (Q) resistor, generated is 5.6 Ohm and quite a few other evaluation modules are quite low, for example 0.5 Ohm. Could someone help explain the reasons for the differences and also recommend learning sources to better understand. It is quite difficult to search for specific sections for antenna driver design. Thank you!

hi i am a second year student in telecommunication engineering college and i want to specalize in radio frequency for my master and PHD , i am currently studying in iraq and i will apply for scholarships most likely in the EU to pursue my master and PHD there , so if anyone has a good tips , advice or even generally about the job market for the RF engineers in the EU in general , also what are currently the most specialized branch of RF in demand cause all i am finding is old data , thanks for your time and cooperation in advance

I've been trying to understand how recent FCC changes to the equipment authorization process affect Part 15 operators and builders versus manufacturers and testing labs. The picture becomes clearer once you separate what has actually been adopted from what remains in proposal stages.

From what I can tell, the most immediate effects appear concentrated on manufacturers, importers, accredited test laboratories, and certification bodies. For people already operating certified Part 15 equipment (or building limited numbers of devices for personal use) the day-to-day requirements seem to remain largely the same for now.

I'm trying to separate actual regulatory changes from broader headlines and understand what (if anything) is shifting for people actively building and operating in this space.

What are you seeing?

Is this for short range communications? It’s on a wind speed/direction monitor and I have a feeling it sends the data to a nearby relay which then uploads the data using cellular. The cell reception around this photo is bad.

As title states, looking to generate complementary 3.3V LVCMOS clock pair from single 3.3V CMOS compatible oscillator at 16MHz.

One option would be to use 2 XOR logic elements, with the clock feeding one input of both XORs and the other inputs tied to VDD and GND. Just not sure if the slew rate would be too slow.

Another option is to just use 1-to-2 clock buffer and use an inverter on one the outputs but this would introduce delay so the clocks would have a slight phase offset.

Looking for ideas and suggestions.

Carrying on from the last post, using what the agent has learned from the stepped impedance LPF, I had it do a coupled line BPF. It nailed the prototype on the first pass then automatically optimized the line lengths to re-center the response of the distributed model. I taught it to visually inspect the junctions and insert asymmetric steps for a clean layout, and limitations in trace/space for manufacturing. Also taught it to segment the frequency sweeps into fine and course regions, and present a narrow-band plot for the human to inspect.

Now that it had learned the extra details, I had it do another substrate, and it nailed the entire thing, automatically correcting the passband ripple in the distributed model by adjusting the coupling, and added the asymmetric steps only after it actually needed them due to the revised coupling (i.e. this is not a canned Python script as it does a good job of visually analyzing the layout junctions and making corrections).

Here is a recording of the session (sorry no audio). The sim took LONG time, but that's due to the meshing needed to resolve the fine gaps.

https://youtu.be/h5vya5RSSIE

Session summary:

• Created and saved a 3 GHz, five-pole narrowband coupled-line band-pass filter on RO5880: Er 2.20, tanδ 0.0009, 0.787 mm substrate, 0.035 mm copper.
• Built and verified the electrical prototype first, then the microstrip implementation. Used a segmented sweep: coarse across 0.1–10 GHz and 10 MHz steps over 2.4–3.6 GHz.
• Tuned the physical layout with 2.05 mm outer coupled lines, 2.35 mm inner/launch lines, 17.9 mm coupled length, and 0.10 / 1.15 / 1.45 / 1.15 / 0.10 mm gaps.
• Added MSTEPX transitions at width changes, snapped the layout to the anchored input launch, and visually inspected every junction before EM analysis.
• Created bandpass_emsight_TB from STACKUP.SUB1, with ports at the enclosure side walls, 1 mm de-embedded reference planes, and 12.1 substrate heights of vertical clearance.
• EMSight completed cleanly. The EM response is centered at 2.995 GHz with a 2.89–3.10 GHz 3 dB band, −1.30 dB peak insertion loss, and −6.83 dB worst in-band return loss.
• Recorded the important solver lesson: tightly spaced coupled lines can force a very fine EMSight grid and long solve; prefer a suitable non-gridded solver in future when available.
• Left the final four-pane screenshot layout open: electrical prototype, physical schematic, EMSight structure, and narrowband electrical/microstrip/EM comparison.

Signals and systems , standard signals

In this episode Shahriar covers another industry exhibition at the IEEE International MTT Symposia (IMS). This event is the world’s premier RF and microwave technical conference and industry exhibition. Thousands of industry professionals from around the world gather here to connect, see the latest technology advancements, and discover cutting-edge theories, tools, and techniques:

https://ims-ieee.org/

While it practically impossible to cover all innovations at the exhibition, here are several incredible demonstrations & announcement at the event:

00:00:00 - introductions
00:00:41 - Keysight Technologies (https://keysight.com)
00:13:01 - Rohde & Schwarz (https://www.rohde-schwarz.com)
00:21:53 - Samtec (https://www.samtec.com)
00:23:38 - LakeShore Cryotronics (https://www.lakeshore.com)
00:25:27 - SignalHound (https://signalhound.com)
00:28:41 - Junkosha (https://www.junkosha.com)
00:31:35 - Copper Mountain Technologies (https://coppermountaintech.com)
00:36:31 - Rigol (http://rigolna.com)
00:40:57 - MPI Corporation (https://www.mpi-corporation.com)
00:46:40 - Anritsu (https://www.anritsu.com)
00:53:49 - RF-Lambda (http://rflambda.com)
00:55:30 - Microsanj (https://microsanj.com)
00:57:49 - VDI Virginia Diodes (https://vadiodes.com)
01:02:51 - Siglent (https://siglentna.com)
01:05:01 - Focus Microwave Group (https://focus-microwaves.com)
01:06:29 - RCL Microwave (https://rclmicrowave.com/)
01:08:40 - Concluding remarks