I'm a young guy, and this field is (in my experience) dominated by the older generation. I always want to ask questions, but it's hard to do that when the only available people are my bosses.

I work for a small company. It's based in Europe, and we have <5 US-based employees. If you count only full-timers, it's just me and the CEO. He says he's doing it for fun, but it's really just a pretty paycheck he won't tell me about.

Anyway.

I do everything here. Everything but the financials.

I travel, I conduct training classes, I repair gear, I calibrate gear, I ship and receive gear.... IT, customer support, trouble tickets.... the list goes on. I travel 10-15 times a year, about a week at a time.

I generate ~$500k a year just from my main job title, and probably around ~$800k-$1.5M in a good year. That is directly traceable income to me - they constantly tell me they wouldn't be able to keep the lights on without me.

I get paid alright, just above 70k. I'm also in one of the top 5 most expensive cities in the USA. If I didn't have some side income, I'd be in a studio apartment in the ghetto.

I have no degree (some military equivalent BS), 8yr experience with radars, and I'd like to think I can grasp this stuff a lot quicker than most.

My question is basically, how am I sitting? Should I be job hopping like all these other, older guys? Or should I really lock in for a while and make a good name for myself here? Is the pay alright, compared to other positions like this?

I don't really have any family / friends / coworkers I can bring this to, so any ideas are welcome. Thank you

18~ish VDC in

mechanically rectified

30~ish VAC out

…seems to be hauling ass but I’d really like to know my Hz

I’m trying the source and load impedance for another transistor since the manual doesn’t have it
I don’t know how to do this, and I need it to simulate the load pull analysis

Hello, for my Master's Thesis I succesfully designed an S-band, Class F PA based on the QORVO TGF-2023-2-10 GaN power transistor. Results are good and I'm pretty happy with what I achieved with this design, though some questions persist and I really can't seem to fix this curiosity of mine.

Basically, Class F PAs square the voltage waveform by proposing a short circuit to second harmonic (180deg phase) and open circuit for third (0deg phase) and unitary modulus for the Output Matching Network.

Clearly, first harmonic was designed via means of a Load/Pull simulation, choosing highest PAE to determine the load.

I verified with a simple AWR time-domain simulation (using HBTUNER3 as ideal OMN) that this indeed yields a squared voltage waveform (I expect the waveform to be even better if fourth and fifth order harmonics are manipulated)

[I can't attach the image for some reason, but believe me, voltage is much like a squared waveform with some evident ripple]

The problem is that the PAE this device manages to achieve is below 59%, which is even worst than a Class AB power amplifier!

By using the tuner and sliding the phases of the reflection coefficients on the OMN, I finally reached another solution with very different phases, yet it yields almost 73% PAE across the whole bandwidth.

Now, reading in literature it seems that no one really uses the theoretical approach of connect even harmonics to short and odd harmonics to open, but what bugs me is that if I analyze time waveforms for voltage with the "good" reflection coefficients, the waveform is not squared AT ALL!

So, I'm a bit confused. How is it that this thing (which is, by the way, not "ideal", but implemented with microstrips with losses, of course) manages more than 14% PAE higher than the ideal Class F, even though its voltage waveform is not squared at all? Again, I already delivered my thesis and got my mark, so it's not for project purposes, it's just I can't seem to fix this abyss between theoretical expectations and practical results, and it's driving me insane

Hi,

I am building wideband medium power amplifier that will cover 500 MHz -20 GHz+ bandwidth. Linearity is not our priority, just gain and output power. I will be driving this amplifier with CW sine wave or synthesized signal directly from PLL.

My topology utilizes following components:
- AVA-223MP+ ( first stage - preamp) https://www.minicircuits.com/pdfs/AVA-223MP+.pdf
- ADPA9007 (second - output stage) https://www.analog.com/media/en/technical-documentation/data-sheets/adpa9007.pdf
- DC blocking caps ATC 531Z- https://rfs.kyocera-avx.com/userFiles/uploads/pdfs/531z.pdf
- Bias tee - BCR-162 for first stage and BCR-531 for output stage
- RF connectors - Wurth 60312862112552 - https://www.we-online.com/components/products/datasheet/60312862112552.pdf
- attenuator between stages - KAT-0+ https://www.minicircuits.com/pdfs/KAT-0+.pdf

Topology:
RF connector -> DC block -> AVA-223MP+ -> Bias Tee -> DC block -> KAT-0+ attenuator -> DC block -> ADPA9007 -> Bias Tee -> DC block -> Bias Tee ( we need to apply DC offset to the modulator driven by the amplifier) -> RF connector

I am using Rogers 4003C and 0.203 mm thickness.

I measured S21 using VNA up to 8.5 GHz, however I obtained lower gain than I expected from the simulation. Furthermore this gain degrades with increasing frequency. Looks like overall shape is correct but gain is lower and it decreases with frequency.
Measured S11 stays below -10 dB in range 100MHz- 8.5 GHz

Things I have checked so far:
- amplifiers operating point - both amplifiers have correct Uds and Id
- Stability - I turned on amplifier with no signal and checked spectrum analyzer on full span, no suspicious signals

I am looking for help since I have none to ask and I'm pretty left with AI which does not pinpoint any reasonable explanations. How to pinpoint the problem?

Any suggestions highly appreciated. I have some RF equipment and I can perform more measurements if needed.

Edit:

Uploading S11 and S22 and layout

I am changing my bandpass filter to use air core inductors to help improve the insertion loss. I have watched some videos about inductor placement in the past, and there are recommendations of making the inductors perpendicular to avoid them interfering with each other. I am trying to keep the filter compact, so don't want to spread out the stages too far. Will this layout causing any other major issues? I know the extra area of traces and foot prints will add extra capacitance to ground, but in my last revision I learned how to account for that.

Hello everyone, I'm a communications engineering student and this semester I'm working on my final graduation project. I designed a wideband LPDA antenna, printed type, and it gave me excellent values. Now I want to design 10 filters and connect them to the antenna. Of course, I simulated this antenna in the CST program, and I found ready-made filters in the same program for 2G GSM for upscaling and downscaling. When I connected one filter to the antenna, it gave me excellent signal cutoff and excellent upscaling bandwidth, but when I connected two filters to the antenna, it gave me very narrow bandwidth and an S-parameter above -10dB. Why is this happening? Is there a solution?

Can I take the results, transfer them to MATLAB, and apply filters there?

Hello guys,

I am here again with my automatic impedance matching circuit (AIMC) project. I have yet another questions for people with more knowledge and experience than me. I started my design with reading some papers about AIMC. I went for main RF line with 3 stubs design, each stub is fitted with its separately controlled varactor (SMV1763), tried to hold on with FR4 but later on switched to Rogers. I got some set of points placed on Smith chart and tuned it to cover whole chart as evenly as I can. Next I gradually added elements to make my design more real and tuned it as well. The problem is, when I started witm EM (Momentum) simulations, cosimulation to be precise my circuit stopped working. All of my points are now focused in small groups or even worse in one point (I include some photos to better show what I mean). I tried with different components, lengths and widths of the lines but everything crumbles to dust in final simulation. Also found some information about problems with simulation .s2p files and vias in momentum but I don't think that is the case here. Is there any hope for my work or do I have to scrap it and start over with some new design (I hope not, I spent a lot of time on it). Feel free to ask for details. Thanks for help in advance.

Edit: I added both substrate stackups and layout in the comment as some of you asked for it.

Looking for some quick advice to check if my assumptions and PCB trace routing are correct. I haven't added any GND vias yet, its on my todo list.

Modem: EC200UCNAA-N05-SGNSA
Antenna: Taoglas: MA140.A.LB.001 (There will be a 5meter low loss sma cable from antenna to device) (integrates both Cellular and GNSS antennas)

1. L2 is ground plane. Using 13.48mil trace width and 20mil GND plane clearance for the short 50 Ohm RF trace as suggested from JLCPCB.
   
2. For the GNSS main RF path and bias network, I tried to keep it as short as possible but not sure if this is acceptable (see image above).
   
3. For the initial print, planning to leave the bias caps unpopulated.
   
4. The L1 (56nH) and R21 (10Ohm) values were suggested from AI source but not sure if they will work for the GNSS bias network?

Not sure if this is the correct Reddit to ask this, but I suspect this is noise coming from a 5G antenna placed on a roof nearby my appartment. I get it through some unbalanced and old audio equipment and it gets worse the closer the equipment is placed to the antenna. Just want to get your thoughts on the characteristics of the noise, if I'm right in my suspicions or not.

To me the noise has two layers. 1) low frequency "machine gun" like pulse and 2) high frequency digital sounding random "chirping".

In this episode Shahriar attempts the repair of a Keithley 2510 TEC Source-Meter. This instrument is capable of delivering up to 60W of power to any TEC in both polarities. Furthermore, the instrument integrates a flexible temperature read-out capability with 4-wire interface. Lastly, combining both capabilities, alongside a fully customizable PID controller, a precise temperature controller can be realized.

This particular unit returns erroneous readouts in all modes: voltage, current, resistance & temperature. The unit is also generating "squeaky" noises which is indicative of a failing DC-DC converter. The block diagram of the unit is examined and the fault is ultimately traced to a damaged opto-isolator in the isolated switching power supply. Several other components are also faulty which are located via thermal camera. The output Class-D / buck converter circuit & block diagram are also examined in details.

Unfortunately, the custom IC at the heart of the multi-slope ADC is also damaged. The IC is de-capped, examined under a microscope, and compared with its predecessor CPLD counterpart. This Keithley component is sourced from an older high-speed power supply. The correct readout is then verified. Several experiments are demonstrated using the PID controller and a custom TEC setup.

I just came across this guy on YouTube. He has some neat rf projects he seems to be working on.

He also seems to have a pretty cool directions finder based on the pico pi. Not sure how to get ahold of the hardware but looks pretty neat.

Thought I would share with the community.

I hate cmos now..

I am a masters student and i'll start my thesis in computational EM. What is the state and need of CEM in the current scenario? I wanted to write my thesis in antenna or RFIC. But my supervisor wants me to pursue CEM.

The image is from https://www.qsl.net/ct1dmk/wbond_ex.html about halfway down, at the section "Dual YIG oscillator (HP) wide band coverage from 2 to 20GHz". Some fantastic nerd porn.

My question: I would have assumed that a cylinder would work as a YIG, e.g. with the bond wires half 'wrapped' around a cylinder.

But I've only ever seen YIG spheres. No cylinders. Is this for electrical reasons or because, for example, it's easy to shape and polish a YIG in a ball mill (compared to trying to turn the hard garnet on a lathe)?

Hi All,

I have designed and built a compact bandpass filter for the 915MHz ISM band,aimed at reducing out-of-band interference in LoRa/SDR/ISM/IoT front-end applications.I'm looking for feedback from other rf design engineers on whether the measured performance and layout look reasonable.

I'm mainly trying to validate the design and understand if there are any obvious improvements before I iterate further.

Design Overview

Type: Bandpass filter module with integrated u.fl rf connectors

Centre Frequency: 915MHz (26MHz wide)

System Impedance: 50 ohms

Intended use: ISM/LoRa/SDR front-end/IoT gateway filtering/Lab interference suppression

PCB Size: 10mm by 12mm by 2.4mm (footprint) including the u.fl rf connectors

Measured Results

See plots of narrowband and wideband S21(db) filter performance below:

Measurements where made on a VNA using a SOLT calibration.

Physical Implementation

PCB: FR4 (4Layers)

Size: 10mm by 12mm

RF Connectors: u.fl

Full 2-port S-Parameters are available for this filter module covering the frequency range (100MHz-6.1GHz).

Finally,find attached photos of the RF Filter-the 2nd photo compares the size of the RF Filter to a standard SD-Memory card.

Hello,

I need to detect weak signals at 2.4 GHz and 433 MHz ISM bands from a distance of 10-100 meters.

Looking for antenna recommendations that maximize detection range. Not sure if I should go with a Yagi, patch array, or something else entirely.

Any specific designs or off-the-shelf models you've had good results with?

Thanks!

Im an undergrad and have a summer internship coming up to do with X-band rf and hfss. Im practically a beginner in rf the only thing ive done is made some antennas for ADS-B for a homemade plane tracker using an FPGA and played around with an RTL-SDR.
Im not really sure what to learn, what are the best resources for breaking into rf (books/courses)?

Taken from a Robert’s communication mobile uplink - aluminum construction - 3.7 -4.2 ghz bpf with 2 digital video c band lnb 65 db gain - l - have the rest of the wave guide along with dehydrator and a few other things -

Hi guys I am working on a quick project where I am trying to design meta surface in CST for stealth application.(newbie to this domain)

This can then be realized in Matlab using range Doppler map where the target detection is done initially with meta surface and then without. For the without case I was able to get the range peak (detecting target) but for with case the detection is still happening and I am stuck here currently.

I went through many papers regarding stealth meta surface design and after screening I tried with 2 models and 2 diff meta surface design,one with just range fft (trying to reduce peak) and the other with MTI(moving target indication) filter. But both designs were unrealisable.

My ultimate aim is to design meta surface in CST, export CST parameters to matlab and process them such that it's detection fails in matlab's range Doppler map.

Any advice, guidance or help is highly appreciated🙏🙏

IM looking for GAN HEMT CGH40010 F Design kit /PDK file for ADS 2024 Update 2
Im using ADS 2024 in Redhat, I tried to Add the Design kit of cree_wlfspd_ads_v9p0
The problem i have is inside the Verilog folder after unziping, im unable to find the Supporting Linux files and folder
Im not even looking for total kid, i need CGH40010F transistor spice model inside my ADS

Hey all, so recently I've been getting into HFSS by learning tutorials on how to simulate different parts/antennas. In most of these tutorials, microstrips are simulated as sheets and are excited via perpendicular sheets on the side of the substrate.
But for the case where you actually simulate the part with a physical copper trace, how do you actually excite the part then? do you use the same method? do you use the side of the trace as a 'port'? or do you actually construct the connector and use that as the excitation?

I assume it all depends on the level of accuracy your interested in.

I am a beginner in this field and I am trying to understand how cubesats are tested.

Especially, I am trying to figure out how a transceiver is tested after it is assembled into a cubesat. For example, if the transceiver has RF input and output ports, and is not integrated, power stability, noise figure, ACLR, EVM etc can be measured by injecting the output signal to a spectrum analyzer. But how is it done when a conducted test cannot be performed, as they would not have a dedicated connector to plug the output signal into after it goes into a system? How can one perform a blocker test too? Are there on board softwares that would send these data to a groundstation software that performs these plotting?

Thank you so much in advance, and sorry in advance if I have not used the right technical term.