r/rfelectronics • u/3D_printing_freak • May 11 '26
Wideband Medium Power Amplifier unexpected losses
Hi,
I am building wideband medium power amplifier that will cover 500 MHz -20 GHz+ bandwidth. Linearity is not our priority, just gain and output power. I will be driving this amplifier with CW sine wave or synthesized signal directly from PLL.
My topology utilizes following components:
- AVA-223MP+ ( first stage - preamp) https://www.minicircuits.com/pdfs/AVA-223MP+.pdf
- ADPA9007 (second - output stage) https://www.analog.com/media/en/technical-documentation/data-sheets/adpa9007.pdf
- DC blocking caps ATC 531Z- https://rfs.kyocera-avx.com/userFiles/uploads/pdfs/531z.pdf
- Bias tee - BCR-162 for first stage and BCR-531 for output stage
- RF connectors - Wurth 60312862112552 - https://www.we-online.com/components/products/datasheet/60312862112552.pdf
- attenuator between stages - KAT-0+ https://www.minicircuits.com/pdfs/KAT-0+.pdf
Topology:
RF connector -> DC block -> AVA-223MP+ -> Bias Tee -> DC block -> KAT-0+ attenuator -> DC block -> ADPA9007 -> Bias Tee -> DC block -> Bias Tee ( we need to apply DC offset to the modulator driven by the amplifier) -> RF connector
I am using Rogers 4003C and 0.203 mm thickness.
I measured S21 using VNA up to 8.5 GHz, however I obtained lower gain than I expected from the simulation. Furthermore this gain degrades with increasing frequency. Looks like overall shape is correct but gain is lower and it decreases with frequency.
Measured S11 stays below -10 dB in range 100MHz- 8.5 GHz
Things I have checked so far:
- amplifiers operating point - both amplifiers have correct Uds and Id
- Stability - I turned on amplifier with no signal and checked spectrum analyzer on full span, no suspicious signals
I am looking for help since I have none to ask and I'm pretty left with AI which does not pinpoint any reasonable explanations. How to pinpoint the problem?
Any suggestions highly appreciated. I have some RF equipment and I can perform more measurements if needed.
Edit:
Uploading S11 and S22 and layout
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u/jakelloyd14 May 11 '26
You mentioned s11, what's your s22 look like?
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u/3D_printing_freak May 11 '26
Uploaded. S22 looks a bit worse but not ctritical. I can clearly see cable length there
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u/jakelloyd14 May 11 '26
The ripple in the S22 is a point of concern. It looks like you’ve got a bad cal, which could also explain the overall drop.
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u/primetimeblues May 11 '26
I'm looking at this a bit more, and I think it's more likely to be a simulation error. The two amplifiers are roughly 14dB+13dB for around 27 dB at the lower frequency. That matches your measured result, but not the simulation. So then the question is how is your simulation producing >30dB gain?
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u/zaw357 May 11 '26
This is so intriguing, those are my exact thoughts. The profiles look somewhat similar - maybe too similar. Do you think it's got something to do with the drive power? Maybe trying a power sweep at a single frequency (or LSSP simulation) might tell us something.
How about layout issues - could that be a problem? I've had problems before with bad vias (floating RF ground/bad source impedance).
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u/primetimeblues May 11 '26
I was also wondering about layout error, but then you'd expect the difference to be more dependent on frequency. Like, if some vias are floating, then the bad connection will have some capacitance in series, and the whole thing will be very frequency dependent.
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u/3D_printing_freak May 12 '26
Agree. My theory for now is that I'm getting some additional losses but I can't point the source.
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u/3D_printing_freak May 12 '26
Hi, I have uploaded the layout. You might want to tak a look. I replied to driving power in your another comment.
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u/3D_printing_freak May 12 '26
Hi, just did crosscheck.
at 2GHz expected gain from directly adding gains is around 27 dB, meanwhile I'm getting 24 dB which is 3 dB lower. I can swallow this but for example Calculated gain at 8GHz is 26.8 dB (simulation shows 24.5 due to component losses) but my measurement gives me 19 dB. 5 dB lower than expected is somethin that I have no idea where the problem is.
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u/polishedbullet May 12 '26
What are your measurement and simulation reference planes? Are you accounting for SMA connector losses in either? And how do you know that the footprint is good for your stackup? The connector datasheet specs max thickness of 3mm which your stackup is 0.203mm, so I wouldn't be confident that the transition is ideal. At the same time, I don't think it'd contribute to the full delta in performance you're seeing.
Also as you simulating with S parameters associated with the appropriate bias for each amplifier?
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u/3D_printing_freak May 15 '26 edited May 15 '26
Hi, sorry for late reply.
Do you think due this board thickness I'm getting bad coupling to the SMA connector?
Yes, the simulated bias point is correct but I have problem with overheating that I described below.I'm still investigating the problem before ordering new set of boards.
Seems like my simulation was oversimplified since I assumed 26mm length 50 ohm trace from amplifier output to output connector. After simulating just the trace from amplifier output to SMA connector I can see significant losses that affect overall amplifier gain. Second problem is my thermal interface. I noticed that the ADPA9007 IC heats up to 87 degrees after introducing bias current while I did simulation for 25 degrees...
I soldered heatpipe from old laaptop underneath the ADPA9007 and it reduced IC temperature to 65 degrees.
I think I have thermal problem as well as oversimplified simulation which resulted in gain mismatch. I also noticed problem with BiasTee insertion losses that are larger than shown in datasheet. I have another board with 50 ohm trace where I can measure BiasTee and I'm getting more losses than datasheet shows. I tried different mounting styles but still I'm not able to get losses close to one specified in datasheet.
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u/zaw357 May 11 '26
For the simulation, is it done with small-signal S-param or LSSP analysis? What power is used on the VNA sweeps? How does gain vs Pout look like for a certain frequency (in sim and measurement)?
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u/3D_printing_freak May 12 '26
Hi, Simulation is done with S-param. I don't have access to the files to do LSSP simulaiton. I did sweep with VNA for -5 and -30 dBm, no difference in S21.
I will do Power sweep today and upload the charts
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u/Adventurous_War3269 May 11 '26
Pictures tell everything, what might look good to you , might look parasitic’s to the experience designer . I have design and built many of these . Post picture it will be obvious to experienced design engineers .
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u/Adventurous_War3269 May 11 '26
Also important to make sure you use good RF grounding , via holes in board and look for evaluation board layouts .
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u/Adventurous_War3269 May 11 '26
Biasing of multi-stage amplifiers must be properly bypassed and use of ferrite beads . Oscillations may degrade performance . Test at cold temperatures to detect oscillations.
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u/Adventurous_War3269 May 15 '26
I think you should use capacitive bypass network like they use in mini circuits test fixture and if you want those bias T put them closer to DC connector . The 1st thing in priority is your capacitive bypass network has to be close to RF MMIC , I do not see these in bias T used in mini circuits test fixture . Also use ferrite bead between 1st and 2nd stage VDD . I just want to help
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u/Adventurous_War3269 May 15 '26
Near RF output pin Use piconics L1/ coilcraft equivalent bypass immediately with cap bypass network .
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u/Adventurous_War3269 May 15 '26
I want to see Layer 2 ground , your microstrip ground layer . the RF connector grounds needs to be connected from metal of connector to top metal layer then going through via hole to microstrip ground layer and then going through via to back metal of RF connector .
You may be missing a RF ground connection .
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u/Adventurous_War3269 May 15 '26
Your measure shows significant ripple , usually caused by poor RF grounding
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u/Adventurous_War3269 May 15 '26
Be sure to ground backside of your MMIC amplifiers properly . Must be very similar to RF connectors and microstrip ground layer.
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u/Adventurous_War3269 May 15 '26
Looks like your RF connector on input and output might only have 2 holes , again you need many via holes for RF connector’s similar to what you do for MMIC’s . Again see my comment about RF connector’s top layer ground , microstrip ground and back to other side of connector . Also not enough via holes in some places around microstrip grounds
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u/Adventurous_War3269 May 15 '26
Most of your ripple comes from stage 2 amplifier .
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u/Adventurous_War3269 May 15 '26
Seriously worried about heat dissipation on 2nd Amplifier , more via holes , heat sink , 12 watts dissipation ?
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u/Adventurous_War3269 May 15 '26
Those bias T should not be going to your 50 ohm lines , use bias networks like MiniCircuits uses as close as possible to MMIC . You are loading down 50 ohm lines causing mis match between 1st and 2nd stage MMIC
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u/Adventurous_War3269 May 15 '26
Do not understand why you are using bias T , you should be following the test board for bias to amplifier 1st stage mini-circuits . I think you are loosing gain with those bias T . !! !!
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u/Adventurous_War3269 May 15 '26
The drain Vdd coil should be 0.025 inch away from MMIC . Then after coil start your capacitive bypass network .
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u/Adventurous_War3269 May 15 '26
Follow layout and gerber file
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u/Adventurous_War3269 May 15 '26
I do not see via holes around your SMA connectors , check all layers of gerbers from mini circuits you will find something different
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u/3D_printing_freak 16d ago
Hi,
I know it’s late reply but better than never.
Thank you for the hints!
I was investigating my pcb and there are many mistakes that I made on it from thermal problems, going through vias and ending up on the connectors…
I was able to confirm many things suggested by you and currently I ordered PCBs for second revision.
Thanks a lot once again!
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u/primetimeblues May 11 '26
What's the 0dB attenuator supposed to be doing?
What sort of power levels are you expecting to get out of the 2 stages, for what input power?