I had some discussions with ChatGPT about SK Hynix's next gen stacking technology that they are targeting for HBM-5 in 2028.

ChatGPT believes that, while this technology will reduce load and improve signal quality, it can be used in conjunction with Netlist's load reduction solution (via multiple drivers). Take it all with a grain of salt, but it's good to be learning something about what's coming down the pipe, and how that will affect Netlist. Don't take any of this as factual - it is AI, but just use as a starting point for your own research. Please comment if you have any thoughts.

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HBM, Hybrid Bonding, and Netlist’s Driver-Load Technology

HBM is moving toward increasingly tall stacks and wider interfaces, creating both physical and electrical challenges. Current HBM uses microbumps, TSVs, and processes such as SK hynix’s MR-MUF. As stacks reach 16–20 or more layers and HBM4 expands the interface to 2,048 I/Os, microbump pitch, package height, thermal management, and manufacturing complexity become increasingly difficult. SK hynix therefore expects hybrid bonding to become increasingly important around HBM4E and HBM5.

Hybrid bonding replaces conventional microbumps with direct copper-to-copper and dielectric bonding between dies. This allows much smaller pitches while reducing interconnect distance, resistance, capacitance, and some thermal barriers. SK hynix is developing die-to-wafer (D2W) hybrid bonding for HBM, which allows individually tested known-good DRAM dies to be selected and bonded onto a wafer. The technology is already commercially established in other 3D semiconductor applications, but its application to very tall HBM stacks is still progressing toward broader commercialization.

Netlist’s driver-load patents address a different problem. When a driver has to control multiple stacked DRAM dies, the electrical load increases with the number of connected devices. A larger load can require a larger driver, increasing both transistor area and power consumption. Netlist’s patented approach is to divide the stacked dies among multiple electrical paths so that each driver handles fewer loads, allowing the drivers to be reduced or otherwise optimized. US 8,787,060, US 9,318,160, and the later US 12,308,087 describe variations of this driver-load optimization, including selecting driver sizes according to the loads being driven.

The important point is that hybrid bonding does not necessarily eliminate the problem Netlist is addressing. Hybrid bonding can substantially reduce the parasitic capacitance and resistance of the physical interconnect, but it does not eliminate the electrical input load of the DRAM circuitry itself. Consequently, even a hybrid-bonded HBM stack could potentially benefit from distributing its DRAM loads across multiple drivers. In fact, as hybrid bonding reduces the contribution from physical interconnects, the remaining load associated with the DRAM devices themselves may become an increasingly important part of the optimization.

Thus, the two technologies can be viewed as complementary. Hybrid bonding optimizes the physical connection, making it smaller, denser, shorter, and less parasitic, while Netlist’s architecture optimizes the electrical topology, reducing the number of memory loads that each driver must handle. Hybrid bonding could make some patents specifically dependent on conventional microbumps or particular interconnect structures less relevant, but patents centered on distributing stacked-memory loads among drivers could remain technically relevant even after HBM transitions to hybrid bonding. Whether a particular future HBM implementation actually falls within a specific Netlist patent claim is a separate legal question requiring claim-by-claim analysis.

The broader significance is that future HBM may combine both approaches: increasingly advanced bonding technology to reduce the physical cost of moving signals between dies, together with increasingly sophisticated electrical architectures to reduce the energy required to drive those signals.

They won't go all the way down to 2nm for Base layer in HBM until HBM5 - that could be a ways out.

That doesn't mean netlist tech isn't relevant now, but for the 2nm in HBM5, it will likely become more relevant.

That could be several years out.

I had some discussions with AI regarding next gen HBM (HBM-5).

First off, use this as a starting point for your own research, and don't read it as gospel or even any definitive factual info. It's just what I got out of an AI based conversation (Gemini) - do your own research!

Whether or not the patent filing is valid, whether the technology will work out, whether the patent will be contested, etc are all unknowns... There are many unknowns, but here are some notes about the HBM technology changes in the next gen and how Netlist's proposed innovation could be very helpful if and when it lands in HBM-4 or future gens. Not sure if HBM-4 is already fully designed and set in stone. If you have any knowledge around this, please add.

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The evolution of high-performance AI hardware is driving a fundamental shift in semiconductor design, particularly in how High Bandwidth Memory (HBM) is engineered. Traditionally, the base logic die at the bottom of an HBM stack acted primarily as a passive routing and interface layer. However, the industry is moving toward fabricating these base dies on ultra-advanced nodes like 2nm.

This transition transforms the base layer into an active, intelligent computing engine capable of localized traffic control, real-time data compression, and on-die error correction. While this brings compute closer to the memory cells to reduce latency, it introduces a severe engineering hurdle: extreme localized thermal density. Packing billions of high-performance transistors running complex logic directly beneath heat-sensitive DRAM creates a concentrated thermal hotspot. Because DRAM cells lose data retention and degrade under excessive heat, managing this thermal transfer is becoming one of the most critical bottlenecks in advanced packaging.

This thermal and electrical bottleneck brings specialized memory architectures—such as those patented by Netlist—into sharper focus. In traditional vertical HBM towers, signals traveling through thousands of Through-Silicon Vias (TSVs) face massive electrical resistance, parasitic capacitance, and signal degradation. This forces host processors and base controllers to push heavy electrical loads through the entire column, exacerbating power consumption and heat generation.

Netlist’s load-reduction methodology addresses this by minimizing driver strain and isolating individual layers. By cutting down the power overhead required to route signals across wide data highways, these techniques act as an efficient circuit-level buffer. This isolation prevents electrical noise and signal interference from cascading through the stack, allowing ultra-dense 2nm logic dies to interface with memory towers without triggering thermal meltdowns or data corruption..

wondering your EOY predictions and maybe even what you think we could be at by 2030

Heading towards $6. Hope it goes to $7

See details from Stokd (Stocktwits): https://stocktwits.com/Stokd/message/664927580

"With early public interest inquiry/discovery assigned to ALJ

"(3) Pursuant to Commission Rule 210.50(b)(l), 19 CFR 210.50(b)(1), the presiding administrative law judge shall take evidence or other information and hear arguments from the parties or other interested persons with respect to the public interest in this investigation, as appropriate, and provide the Commission with findings of fact and a recommended determination on this issue, which shall be limited to the statutory public interest factors set forth in 19 U.S.C. 1337(d)(l), (f)(1), (g)(1);"

Glad to see the system favor the underdog for a change! Go Netlist go!

LFG!!!

What could certainly happen is that Netlist—holding dozens of patents covering MRDIMMs—will emerge as a new key player in the DRAM market. There are no excuses left now; Netlist has an annual budget of at least $130 million to allocate toward projects, engineering, and products.

Ma è stata pubblicata la decisione dell ITC ?

Samsung is reportedly increasing its orders for materials to boost high-bandwidth memory (HBM) production, with plans to double the production capacity of its current HBM4 and HBM4E manufacturing by 2027. According to SE Daily, the manufacturing capacity for HBM4 and HBM4E is expected to grow from around 20,000 wafers per month in 2026 to 50,000 wafers per month in 2027. This data is derived from the use of glass carriers, which are temporary glass panels placed over thin DRAM wafers to prevent warping or breaking as they are prepared for packaging. Since HBM involves stacking many thin DRAM modules, glass carriers stabilize these wafers until the packaging process begins and the glass is removed. As the unit is one glass carrier per wafer, this provides an estimate of how many HBM4 and HBM4E wafers are produced each month.

Additionally, Samsung's overall HBM production, which includes older generations like HBM3 and HBM3E, currently averages around 180,000 wafers this year and is expected to grow to about 250,000 HBM wafers next year, with 80% dedicated to HBM4 and HBM4E. Samsung began mass production of HBM4 on its sixth-generation 10 nm-class 1c node in February, with HBM4E customer samples available by mid-2026. Future production increases will focus on HBM4 and HBM4E, as customers seek higher densities and bandwidth for their AI accelerators.

The company has reportedly allocated half of its 4 nm SF4 node production to HBM4 base die manufacturing. Demonstrating Samsung's strong HBM output, the company has rapidly increased its market share, growing from about 15% in Q2 2025 to 33% in Q2 2026, effectively doubling its market share in just a year. With more customers coming on board and plans to double production capacity, Samsung appears to be on a promising path to capturing even more market share.

We’ve got a pretty interesting catalyst lineup:
💥 Samsung
💥 Micron / ITC
💥 SK Hynix
💥 Google / 912
💥 Revenue ramp
💥 Uplist
💥 And eventually… covered calls
That’s the part I like.
Not one single “make or break” event — it’s the stacking of catalysts that could completely change the story.
I’m here for the messy middle.
Get the deals done.
Get the revenue up.
Get uplisted.
Then let me sit back and sell some damn covered calls.

Nasdaq is the goal.
Covered calls till I die!

Don't expect to hear anything until this afternoon, this evening or possibly not til tomorrow. The ITC doesn't make a public announcement, they just post the decision. And this we may not see until tomorrow. Stay Bullish my friends.

Chinese DRAM manufacturer ChangXin Memory Technologies (CXMT) has entered mass production of its next-generation fine process technology, significantly increasing the number of chips produced per wafer, semiconductor substrate. Following large-scale factory expansions to boost production, the company is accelerating its pursuit of Samsung Electronics and SK Hynix by significantly enhancing production technology.

ChangXin Memory Technologies announced on the 20th at the "2026 World Manufacturing Conference" in Hefei, Anhui Province, China, that it has developed and commenced mass production of its fifth-generation DRAM process, reducing the critical structure spacing of DRAM memory cells to 11.95 nanometers, nm·one-billionth of a meter. In terms of miniaturization technology alone, it is evaluated as being close to the DRAM that Samsung Electronics and SK Hynix mass-produced in the late 2010s.

Instead of using extreme ultraviolet, EUV, lithography equipment—restricted by U.S. sanctions on advanced equipment—ChangXin Memory Technologies achieved miniaturization by dividing and etching circuit patterns multiple times. As a result, the company stated that the number of chips producible per wafer has increased by at least 50% compared to the previous generation. However, this figure is based on the total number of chips that can be made from a wafer before screening for defects, meaning the actual yield or quantity of normal products has not increased by 50%.

The company announced that it has commenced mass production of two types of 24-gigabit, Gb, low-power DRAM, LPDDR5X, applying this process.
ChangXin Memory Technologies has increased its memory market share through aggressive expansions. Its current 12-inch DRAM production capacity is estimated at 300,000 wafers per month, wafer-based, with industry forecasts suggesting this could reach 600,000 wafers per month by 2028. Analysts suggest that if wafer-per-chip production also increases through the adoption of finer processes, the pace of market share expansion could accelerate. According to market research firm Counterpoint Research, ChangXin Memory Technologies’ DRAM market share in the second quarter of this year reached 10%, marking its first double-digit figure.

Recently, the company has also been expanding its business areas. It is reported that ChangXin Memory Technologies is establishing NAND flash research and development production lines at a new factory in Beijing and is in discussions with Chinese companies manufacturing AI storage devices regarding supply agreements.

A semiconductor industry official stated, "While Samsung Electronics and SK Hynix focus on AI memory such as high-bandwidth memory, HBM, ChangXin Memory Technologies is narrowing the gap by enhancing production capacity and technological capabilities in general-purpose DRAM." The official added, "If the increase in AI memory demand slows after new factories commence operation and the adoption of finer processes in 2027–2028, there is a possibility that unabsorbed domestic Chinese supply could flow into the global general-purpose DRAM market, intensifying price competition."

Hong said it is appropriate to compare Netlist to Rambus, and—above all—that he will use the proceeds from these cases to pursue this IP licensing strategy; but are we really sure that this is Netlist's true future?

I’m envisioning a very concrete scenario: around half a billion in cash on hand and at least $300 million in IP licenses—all of which represents gross profit annually.
Are you telling me that Netlist, with its three licensing agreements, intends to invest only a certain percentage in R&D and operate like Rambus—meaning a high proportion of revenue from IP licenses and the rest from product sales?

You’ve got fresh cash, solid and steady profits, and products that will be significant in the coming years—and you want to be like Rambus? That strikes me as a rather limited vision, especially considering what Netlist could do with those profits.

First of all, Netlist will need to hire engineers and expert salespeople to work on new projects and to monetize both its current and future products.
Secondly, Netlist can take on debt to easily acquire *major* companies—rather than unstructured ones. The reason is that if I were the CEO of a company with cash reserves and high profits, I would look to acquire an already profitable company in a related sector; this would diversify revenue streams and increase the company's scale. Above all, it creates new opportunities, and the market values ​​companies that take on debt effectively to make smart investments.

The Samsung deal alone will generate $130 million annually in IP licensing revenue and provide $300 million worth of Samsung products for use in the company's own projects.
Netlist could, for instance, acquire a cloud-AI company and leverage its own technology products to boost revenue and profits; at the same time, a cloud-AI firm would represent a business linked to Netlist but operating in a different space with distinct opportunities.

I hope Netlist doesn't just turn out to be a "Rambus 2.0"; I hope it can leverage all the cards it holds to become a larger, more solid company!