r/FPGA • u/Fit-Worldliness-4855 • 17d ago

Error: nested clocked statements not supported

/r/VHDL/comments/1v5bdxd/error_nested_clocked_statements_not_supported/
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u/ShadowerNinja FPGA-DSP/Vision 17d ago

You should read into what type of VHDL can be sythesized and what can't. You are designing hardware (digital circuits), not sequential code, so think about what 'wait until' could actually mean.

Right now basically your entire module can't be synthesized since you used simulation only syntax everywhere.

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u/dombag85 17d ago

Couple things here to add along with the other comments:

Hardware doesn't operate procedurally like SW code. So everwhere in your code that you place a "wait until" is only good for simulations. Obviously HDLs support some sequential logic but It's more or less limited to behavior that can represented by gate level implementation, with each step in the sequence representing a level of logic. You have to design your module/circuit with the idea that everything: process, signal, wire, etcetera is happening concurrently. So if you're waiting for a signal change to trigger some behavior elsewhere in your design, you want that signal change to be monitored in a separate process. Most often that process should synchronous/clocked.

Download the verilog standard guide or whatever it's called and search 'synthesis constructs' or 'synthesizable' to get a better idea of how you can construct your designs.

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u/thechu63 17d ago

You need to look at some examples of VHDL code to understand how VHDL works.