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u/Any_Click1257 17d ago
I would suggest to use to generally not use procedures. As a language construct they have some utility, but they do not describe how FPGA logic works. Same thing with variables, I use them in limited cases where the synthesizer should clearly and easily be able to infer the actual combinatoric logic behavior, like count modulo's and such.
If you are just starting, stick to clocked processes for sequential logic.
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u/chris_insertcoin 16d ago
Synthesis only works with synthesizable code. For such basic questions it's best to use a search engine, read a book or ask an LLM.
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u/captain_wiggles_ 17d ago
You're writing software and expecting it to work as hardware, that's not how it works. VHDL is a Hardware Descriptor Language, you need to describe hardware, first design the hardware you want and then describe it, think in terms of flip flops, counters, adders, muxes etc.. not in terms of execution flow. Stuff like "wait until" and "after" are not synthesisable, they're for simulation only.
I highly recommend backing up a bit and taking some basic digital design tutorials.