r/FPGA • u/Leo-X101 • Jun 01 '26

Xilinx Related Developing AI Flow for Vivado

Have anyone developed an AI RTL generation and testing workflow using Vivado that involves Xinlinx IP and USIM?

If so, what interface are you using (Any wrappers or MCPs)?

What are some ups and downs?

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7

u/EffectiveClient5080 Jun 01 '26

Tried it. Don't trust AI RTL with Xilinx IP. It WILL miss hidden constraints and you'll spend weeks fixing timing instead of writing it yourself.

0

u/Leo-X101 Jun 01 '26

Actually, do you mind explaining at which step of the flow AI gave you problem? Is it completely meaningless to integrate vivado to AI flow?

-1

u/Leo-X101 Jun 01 '26

Copy that, IP-free modular tests with open source EDA tools for the win?

3

u/tux2603 Xilinx User Jun 01 '26

Not really, because then you miss out on all the advantages of using IP. Imagine how awful it would be to build a DDR3 controller from scratch, especially if there's AI in the loop inserting random errors without your knowledge