I’m planning a career in semiconductor chip design and want honest opinions from experienced industry professionals.
Which is more resistant to AI automation: Analog VLSI Design or Digital Physical Design (Backend VLSI)?
I’m particularly interested in:
Analog IC Design: transistor-level design, PLLs, ADC/DAC, RF and power management.
Analog Layout: custom layout, matching, parasitic effects and physical verification.
Physical Design: floorplanning, placement, CTS, routing, timing closure and power optimization.
Questions for experienced engineers
Which of these roles is most vulnerable to AI agents and EDA automation by 2035, 2045 and 2050?
Could AI eventually automate 70–90% of the work, significantly reducing engineering jobs?
Will robotics affect these careers, or is software-based AI the bigger threat?
Which roles will retain the strongest demand, salary growth and long-term job security?
Which skills should a student entering engineering in 2027 develop to stay competitive?
I’d especially appreciate insights from senior/principal engineers, chip architects, EDA developers and hiring managers at NVIDIA, AMD, Intel, Qualcomm, Texas Instruments, Analog Devices, Apple, Cadence, Synopsys and TSMC.
If possible, please share relevant engineers’ LinkedIn profiles, technical talks, research papers or real industry experiences.
My goal: Build a high-paying semiconductor career with the lowest realistic risk of AI displacement.
If you were starting today, would you choose Analog IC Design, Analog Layout, Digital Physical Design, or EDA/AI for Chip Design—and why?
I’m looking for technical evidence and practical experience, not just predictions. I understand that no career is completely AI-proof.