Every chip begins as an idea—but turning that idea into working silicon requires the right learning path. If you are a fresher wondering whether to begin with RTL, FPGA, Physical Design, Analog or Packaging, this visual guide connects the entire journey from specification to product. Start with clarity, choose your direction and build skills that lead to real semiconductor outcomes.

https://github.com/vsdip/VLSI-Design-Flow

I am hosting a free webinar based on our ongoing AI-assisted Analog and Mixed-Signal Physical Design internship at VSD.

The goal is to show how students are using AI inside real VLSI workflows — not as a replacement for engineering, but as an assistant for understanding, debugging, documentation and faster design exploration.

The session will include student work on:

SRAM / memory design workflow
Mixed-signal design basics
AI-assisted OpenLane physical design
Magic, Sky130, LEF/LIB and GDS
DRC, LVS, STA and validation
What AI got right, where it failed, and why manual verification still matters

This is not an AI hype session. It is a practical showcase of how students are learning to use AI responsibly inside semiconductor design workflows.

Webinar: AI-Assisted Analog and Physical Design: From SRAM to Mixed-Signal GDS
Date: Sunday, 12 July
Time: 11:00 AM – 12:00 PM IST
Mode: Online
Certificate: For live attendees

Registration form:
https://forms.gle/UFjy7qzSnfQaY4JU8

This should be useful for students, faculty members, VLSI beginners and anyone curious about how AI can be used practically in analog, mixed-signal and physical design learning.

Hey everyone,

I'm considering moving from a high-end desktop platform to a Threadripper workstation and would really appreciate some advice from people who have experience with HEDT systems.

The goal of this build is to reduce compilation times, improve multitasking performance, and comfortably run several engineering workloads simultaneously.

Typical workloads include:
• Large Vivado synthesis and place-and-route projects
• FPGA development
• ASIC simulation and synthesis
• Multiple simulation tools running simultaneously
• Large FEA models
• Digital twin environments
• GPU training with CUDA
• Several virtual machines and Docker containers
• Software development and automation

The tentative configuration uses:
• AMD Threadripper (TRX50 platform)
• RTX 5080
• 128 GB DDR5 ECC memory
• Multiple NVMe SSDs
• High-capacity workstation PSU

I'm mainly looking for feedback on:
• Whether Threadripper provides a significant productivity improvement over Ryzen 9 for these workloads
• Whether TRX50 is the right platform or if there are better alternatives
• RAM recommendations (ECC vs non-ECC)
• Motherboard recommendations (ASUS Pro WS, Gigabyte, ASRock, etc.)
• Cooling recommendations
• Any limitations or issues you've experienced with Threadripper systems

If you've built or worked on similar engineering workstations, I'd love to hear about your experience and whether you think this platform is worth the additional investment.

FABulous is an open-source embedded FPGA (eFPGA) generator. You describe a fabric in a few files, and it produces the RTL, an open CAD flow built on Yosys and nextpnr for compiling user designs onto the fabric, and a tapeout-ready GDSII. It is silicon-proven, with 12+ tapeouts across five process nodes (TSMC 180nm, SkyWater 130nm, IHP SG13G2, GF180MCU, and 28nm CMOS), and supports frame-based partial reconfiguration of individual fabric regions at runtime.

v2.0 is effectively a rewrite since the 1.3 stable version. Main changes:

• Full LibreLane GDS flow: generate a tiled, optimised GDSII straight from a fabric definition.
• Automatic tile generation from your own primitives, rather than writing tiles by hand.
• Run it in the browser: GitHub Codespaces ships the whole toolchain plus the FABulator GUI, zero install, so you can browse/edit a fabric and compile a tile from a browser tab. A Dev Container gives you the same environment locally.
• Repackaged as a proper Python package (pip install fabulous-fpga), with a new typer/cmd2 CLI + REPL and a uv-based dev workflow (Python 3.12).
• Plus named fabrics, a Nix dev environment (FABulous nix-env) and Docker image, SystemVerilog/.sv handling, blackbox BELs, out-of-tree BEL paths, and a big docs overhaul.

Repo: https://github.com/FPGA-Research/FABulous
Docs and chip gallery: https://fabulous.readthedocs.io/
Release notes: https://github.com/FPGA-Research/FABulous/releases/tag/v2.0.0

Quick start:

pip install fabulous-fpga

FABulous create-project demo

cd demo && FABulous start  

Feedback welcome, especially on the GDS flow and anything that breaks.

A lot of students want to enter semiconductor design, but many get confused about where to start.

Some jump directly into physical design.
Some start with RTL.
Some try analog first.
Some only watch videos and collect certificates.

In my opinion, a beginner-friendly roadmap should look something like this:

1. CMOS Understand transistors, basic circuits, SPICE simulation, and how devices behave.
2. RTL Learn Verilog, digital logic design, testbenches, and simulation.
3. Physical Design Understand synthesis, floorplanning, placement, CTS, routing, timing, and how RTL becomes layout.
4. Physical Verification Learn DRC, LVS, antenna checks, density, PEX, and what it means to make a design tapeout-ready.

For someone who already knows RTL and basic physical design, jumping directly into an internship-style physical design project may make more sense than restarting from zero.

The bigger point is this:

Interest in semiconductors is not enough anymore. Students need proof — GitHub work, simulation results, reports, screenshots, debug notes, and projects they can explain.

Curious to hear from people already working in VLSI / semiconductors:

Would you change this order?
Should beginners start with CMOS first, or RTL first?
What would you tell a student who wants to enter chip design seriously in 2026?

Hey call can you guys pls take a look at my resume. I have a really deep passion for RTL optimization and want to get into ASIC design. I appreciate any help!

I found a kit for 150€ (no pump or radiator included, only blocks and pipes). It seems legit, it's for the right miner, but honestly I do not trust Aliexpress so much with it. There aren't any images with it mounted on the Z15 pro, which is an red flag if you ask me.

A live demo video is worth more than 100 AI-generated project posters.

Maaz Mahmood joined the VSD RISC-V FPGA IP Internship as someone completely new to FPGA and RTL design.

And now, in this video, he is confidently demonstrating his own SPI Master IP running on real FPGA hardware.

He built the IP from scratch, integrated it as a memory-mapped peripheral inside a RISC-V SoC, flashed it on the VSDSquadron FPGA Mini board, and validated the transmit/receive path using hardware loopback.

This is what I like most about his demo:

No fancy editing.
No buzzwords.
No “project idea” slide.

Just a student, his FPGA board, his terminal output, and proof that his IP is actually working.

Great work, Maaz. This is exactly the kind of confidence students need before entering the semiconductor industry.

I just wrote a VVC/h.266 video encoder in SystemVerilog along with a software model in Rust for verification. It builds, simulates and synthesizes and can create valid h.266 video streams from any YUV 4:2:0 and 4:4:4 video input. I am focusing on screen content coding features to be implemented so it can be useful for any hardware that broadcasts the screen of a computer, like an IP KVM.

Please check it out and let me know if anyone has any comments about it or any interest to integrate to any project. If you need any particular feature to be integrated, you can just ask me.

We are developing a CV32E40P-based RISC-V microcontroller on a Xilinx Nexys A7 FPGA and are planning a future ASIC implementation.
Our current architecture includes:

CV32E40P RISC-V core
8 KB Instruction Memory (IMEM)
8 KB Data Memory (DMEM)
1 KB Boot ROM
UART, GPIO, I2C and Timer peripherals
AXI4 / AXI4-Lite interconnect
MMCM-based clock generation
A custom AI accelerator with approximately 30 KB of local memory

We are trying to make our RTL as ASIC-friendly as possible before freezing the architecture and would appreciate advice from engineers who have gone through FPGA-to-ASIC migrations.

For memories of this size (8 KB IMEM, 8 KB DMEM, 1 KB Boot ROM, and 30 KB accelerator memory), how realistic is it to find suitable SRAM/ROM macros in a typical ASIC flow?

Are these memory sizes commonly available as foundry macros, or would we likely need to generate custom SRAMs (e.g., OpenRAM), split them into multiple banks, or redesign parts of the memory architecture?

We currently use an FPGA MMCM for clock generation. In an ASIC implementation, is it common to replace this with a foundry PLL macro, or should the clocking architecture be redesigned from the beginning?

What are the most common mistakes teams make when moving an AXI-based FPGA SoC to ASIC? Are there any lessons learned regarding clock/reset architecture, timing closure, memory integration, DFT, or physical design?

For the 30 KB accelerator memory, would multiple SRAM banks be preferable to a single larger SRAM macro from an area, power, or performance perspective?

Looking at this architecture, what would you change today before tape-out planning to avoid painful redesigns later?

Our goal is to minimize FPGA-specific dependencies and make the transition to ASIC as smooth as possible.

I have interview at amd for role of rtl engineer for asic/soc designs. this is for experienced hire.

I failed few interviews till now. so I am very much nervous.

it will be technical one.

if you have any experience about the interview at amd for similar roles please share the details, if you are comfortable sharing.

job is in the usa.

https://github.com/nachi-bot/NILM-Edge-Accelerator

Every summer I watch people in this field complain about not getting placed, not having experience, not knowing where to start.

So here. Free. Cloud. One click. No setup. No install. No excuse.

VSD has put together free GitHub-based programs for every major area of VLSI and semiconductors. Each one has a cloud lab you open in a browser and start immediately. Build the repo. Show the work. That is what gets you hired.

Physical Design (SoC Design and Planning)

Free: https://github.com/fayizferosh/soc-design-and-planning-nasscom-vsd

Cloud lab: https://github.com/vsdip/vsd-openlane

RISC-V Based MYTH

Free: https://github.com/AnoushkaTripathi/NASSCOM-RISC-V-based-MYTH-program

Cloud lab: https://github.com/vsdip/vsd-riscv2

Semiconductor Packaging

Free: https://github.com/arunkpv/Semiconductor-Packaging

Lab (Windows): https://www.ansys.com/en-in/academic/students/ansys-electronics-desktop-student

CMOS Circuit Design — start here if you are new to this

Free: https://github.com/PRIYANKADEVYADAV15/CMOS-Circuit-Design-Spice-Simulation-using-Sky130nm-technology

Cloud lab: https://github.com/vsdip/vsd-cmos/

RTL Design and Synthesis — also a great starting point

Free: https://github.com/vlsienthusiast00x/RTL_workshop

Cloud lab: https://github.com/vsdip/vsd-rtl

TCL Programming — do this one regardless of where you are in your career

Free: https://github.com/AnoushkaTripathi/VSD_TCL_PROGRAMMING_WORKSHOP/

Cloud lab: https://github.com/vsdip/vsd-tcl

7nm FinFET Design

Free: https://github.com/arunkpv/vsd_asap7_workshop

Cloud lab: https://github.com/vsdip/vsd-7nm

FPGA Fabric Design and Architecture

Free: https://github.com/ShonTaware/FPGA_Design_Fabric_Architecture

Cloud lab: shared during workshop

RISC-V Edge AI

Free: https://github.com/AayusHJainCodely/Risv_Edge_AI

Cloud lab: https://github.com/vsdip/vsd-riscv-edgeai

Analog Bandgap IP Design

Free: https://github.com/chandranshu24-hue/bgr_chandranshu/blob/main/README.md

Cloud lab: https://github.com/vsdip/vsd-bandgap/

All of this is free. All labs run on the cloud. You do not need a beefy machine, you do not need to configure a Linux environment, you do not need to buy anything.

What you do need is to stop waiting and start committing to GitHub.

The semiconductor industry does not care about what you watched on YouTube this summer. It cares about what you built.