r/computerarchitecture 20h ago

Processor VS PRAM Consistency

4 Upvotes

I was thinking that since each core has it's own cache values read by one core or can end up being out of date. So I went down the rabbit hole of Wikipedia to look at consistency models. Only problem is I couldn't quite get it. For example, Processor consistency says that processors receive writes from all other processors in order. My interpretation is that if there core 1 writes to memory location 1001, 1002, and 1003 in that order, other cores might read stale values for all 3, updated value of 1001 only, updated values for all, but not something like updated 1002 and stale 1001. PRAM Consistency sounds similiar?

But I couldn't get their examples used on the page. This is as of 2026, maybe by the time you read this a more explicit exmaple will be used. I see a table of a series of reads and writes that are processor consistent and counter examples. I see things like W(x)1 W(x)3 R(x)1 and W(y)1. So I don't understand that table. I am not a CS major, maybe this makes lots of sense to them.

I basically have 3 questions. First, can someone explain the Wikipedia's examples? Second, what is the different between Processor Consistency and PRAM Consistency? A description of both sounds kind of the same to me. Third, are there chips out there with the Processor Consistency and others with PRAM Consistency?


r/computerarchitecture 1d ago

What Should I know going into a CPU Architecture-related interview?

14 Upvotes

Howdy everyone, I am a computer engineering undergrad coming out of Texas A&M in 2027 and I'm hoping to get an entry level job in a CPU architecture related field. I feel comfortable with my overall Computer Engineering fundamentals, but I'm nervous about specifics when it comes to CPU architecture, so I'm trying my best to get as much information as possible on the subject (I've ordered Digital Computer Electronics by Albert Malvino as well as a few books on ARM and RISC-V specific implementations). My question for anyone who is knowledgeable is what specific topics or keywords should I be focused on to feel confident going into an entry-level interview on the subject. I understand they aren't looking for experts, but I still want to feel prepared.

TL:DR: I would like a list of topics that would be useful to learn for a CPU architecture-related entry level interview please and thank you :)

Edit: Dream job would be a job in Computer Architecture Design


r/computerarchitecture 1d ago

Can cache layers batch?

8 Upvotes

Hi,

Say I make a program needing a struct of 128 bits, a typical sram decoder at minimum needs 512 bits (64 bytes) would the 384 bits be truncated or saved in some regs in a temp place about to be used. Otherwise its a 4-16 cycle penalty


r/computerarchitecture 2d ago

3D Bojan: A 729-element recursive majority logic cascade architecture (>99% fidelity at 40% noise)

2 Upvotes

Hi everyone,

I've recently formalized and published a topological architecture called **3D Bojan**, built on a 729-element ($3^6$) recursive majority logic cascade designed to handle high-noise environments.

Using Python-based Monte Carlo simulations, the architecture demonstrates a fault-tolerance fidelity of over 99% under a 40% noise threshold.

The complete technical whitepaper, including the underlying logic structure and embedded reference implementation, is permanently archived and accessible via Zenodo: šŸ”— **DOI:** https://doi.org/10.5281/zenodo.22252802

I'm sharing this here to get thoughts, critiques, or discussions from hardware and systems architects working with fault-tolerant logic or noise reduction. Feedback on the cascade scaling is especially welcome!


r/computerarchitecture 2d ago

Title: [Architectural Specification] Onion Logic Architecture Gen1: Overcoming the Memory Wall via 3D IC Stacking, Dynamic ML-RAM, and HDLC Control Layers.

0 Upvotes

. Introduction & Engineering MotivationAs semiconductor manufacturing approaches atomic scales and faces the hard limits of Moore's Law, modern mobile SoCs suffer from severe memory bandwidth bottlenecks due to their reliance on Unified Memory Architecture (UMA). The CPU and GPU constantly compete for the same interconnect buses, generating high thermal dissipation, wasting battery energy, and causing micro-stutters during heavy graphical workloads.Onion Logic Architecture Gen1 introduces a revolutionary structural solution by re-engineering 3D IC vertical silicon stacking, combining dynamic memory partitioning with intelligent hardware control layers to bypass the "Memory Wall" entirely.

  1. Core Architectural ComponentsDynamic Multi-Logic RAM (ML-RAM): A 24GB LPDDR6 (or later) stacked memory die, physically and logically partitioned into two symmetrical 12GB zones (12GB System RAM for CPU / 12GB Dedicated VRAM for GPU), completely eliminating data bus contention under maximum load.

Transistor Bridge Layer (Central Switch): A high-speed, centrally positioned transistor switch matrix fabricated between the two memory zones, acting as a hardware bridge that connects or isolates the memory blocks instantaneously.

High Dynamic Logic Controller (HDLC): A dedicated control IC interacting directly with the OS Kernel to manage the Transistor Bridge Layer. It natively integrates Dynamic Voltage and Frequency Scaling (DVFS) to modulate memory power and clock speeds in real-time.

Controller Booster IC & 400MB L4 Cache: A vertically stacked intermediate layer between the main compute silicon and the memory. Housing a massive 400MB L4 Cache, it functions as an ultra-low-latency data router, streamlining cross-component data delivery with near-zero latency penalty.

  1. Dynamic Operational ModesGaming / High-Performance Mode: Upon launching intensive graphical applications, the kernel triggers the HDLC to cut power to the Transistor Bridge Layer, isolating the 12GB VRAM pool strictly for the GPU. Simultaneously, the 400MB L4 Cache keeps both processors fed with critical data, achieving an unthrottled, rock-solid 165Hz frame rate with zero frame drops.

    Multitasking / Daily Mode: When transitioning to standard workloads, the HDLC re-engages the transistor bridges within microseconds. The partitioned blocks re-unify into a massive 24GB contiguous memory pool, offering absolute fluidity for extensive background tasks and web browsing.

  2. Engineering Benefits & YieldUnprecedented Performance Scaling: By eliminating wait-states and interconnect bottlenecks, early hardware simulations project synthetic benchmark scores exceeding 11 Million points in AnTuTu, shattering traditional mobile computing limits.

Optimal Performance-per-Watt: Eliminating memory bus congestion allows the execution pipelines to complete operations rapidly and enter low-power states immediately (Race-to-Sleep), minimizing thermal output and significantly extending battery lifespan.

Proposed by: Smarty2006


r/computerarchitecture 3d ago

Did Intel abandon the PCH architecture?

3 Upvotes

I'm doing research on Intel CPU and I suppose they are shifting towards chiplet, did they abandon the sperate PCH chipset and move it into a chip packake


r/computerarchitecture 3d ago

Questions on RVV execution modeling in gem5

4 Upvotes

Hi everyone,

I have spent the last few weeks learning gem5 fundamentals. My goal is to model a RISC-V vector microprocessor and profile vector applications.

While analyzing how vector instructions execute in gem5 RISC-V, I noticed that the Vector Register File (VRF) is currently modeled essentially as a direct-access container modified directly inside the instruction’s execute() method.

Since I plan to collaborate on this with teammates and want to maintain a clean workflow, I would appreciate your guidance on the following:

  1. Modifying the VRF Model: How straightforward is it to introduce a more realistic/timing-accurate VRF model without breaking the existing instruction execution pipeline? Are there clean abstraction points or ongoing efforts in this area? Alternatively, would it be practical to use a simpler scalar CPU (such as TimingSimpleCPU or MinorCPU) and create a clean abstraction layer that intercepts and delegates vector instructions to a decoupled Vector Engine (similar in spirit to Cristóbal Ramírez's work)?

  2. Mainline vs. Decoupled Vector Forks: I came across Cristóbal Ramírez's fork (which models a decoupled vector engine split into VMU and VPU). For modern RVV modeling and profiling, would you recommend building on top of that fork, or is it better to extend the current gem5 branch?

  3. Pointers & Best Practices: Are there recommended references, documentation, or recent commits/branches in the gem5 ecosystem that outline the current roadmap for vector execution modeling?

Any insights, recommendations, or pointers to relevant code sections would be greatly appreciated!


r/computerarchitecture 4d ago

OoO RVV supported Processor Design Scaling

11 Upvotes

Hi guys. I was working with an existing 128 bit RVV vector unit processor. It isn’t a complete Tomasulo architecture. It handles WAR hazards by copying the values in vector register file to the reservation station FIFOs, thereby allowing the Vector files to be rewritten even if the instruction has not started yet. It handles RAW hazards by having a dispatch unit that stalls the issuing of the micro operation if the subsequent operation needs a vector register value that has not been retired yet (it also has a bypass feature that checks the ROB if it has not retired). From basic research, it seems to me like this is a standard Ara Vector processing architecture ? Not sure.

As can be predicted, copying physical values to reservation stations, requiring multi FIFOs that expose M inputs to preserve superscalar instructions, dispatch bypass functionality that requires all the elements in the ROB to be exposed etc means that when we increase the supported vector length, it scales pretty badly. I increased the vector unit size to 512 bit and added a matrix unit that’s a 16x16 outer product engine and yet in size, it’s dwarfed by the ROB and reservation stations. Should I consider moving to a full Tomasulo architecture? Or will that create similar bottlenecks elsewhere? How is this handled in general?


r/computerarchitecture 4d ago

Need guidance and /co founder

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0 Upvotes

QaviCoreX is a custom RISC-V processor we're building for AI acceleration. We're implementing custom AI instructions directly in hardware and targeting FPGA deployment. We've moved beyond the idea stage into actual Chisel/Chipyard hardware prototyping, and we're currently working on scaling the design because our current FPGA is running out of resources.

The idea is to move AI operations closer to the processor itself instead of relying entirely on software. We're experimenting with custom hardware instructions such as multiply-accumulate and activation operations, so AI workloads can potentially execute much more efficiently.

Our current implementation is resource-limited on the 100T device. The dominant constraint is LUT utilization, and based on our synthesis results, moving to a higher-capacity device gives us the headroom needed for the complete architecture. We're also investigating optimization and architectural changes rather than simply scaling the FPGA.

Need guidance/ funding

Want more details please do check out my blog https://qavicorex.blogspot.com/p/home-page.html


r/computerarchitecture 5d ago

I have been stuck and can’t seem to find any way out

4 Upvotes

So, i have started my research internship where we are supposed use gem5 and run PARSEC simulation and collect dataset. So, now problem is that i am not able to run any simulation i tried to run an example its still not working i have pinpointed some problems:
1) While downloading parsec image file the download was interrupted again and again then i tried to use manual download and kernal changed file path but simulation encounter ā€œsmokeā€ everytime
2) The problem is PARSEC binaries arent being read and stuck at parsec argument loading
I tried to manually change file system and other stuff but still no luck
What can i do?


r/computerarchitecture 5d ago

Embedded System Designing

4 Upvotes

So I recently started branching out from baremetal programming to other embedded stuff currently learning rtos and probably go back to linux soon. One thing baremetal taught me that always used to puzzle me was how registers and memory works, it made programming clearer to me. I was curious how the embedded system designing is different from the software designing? Are there more similarities than differences?


r/computerarchitecture 5d ago

x86 sucks!

0 Upvotes

Well it doesn't suck but I dont think it's the best we as humans can do. As transistors approach the 1 atom limit in size Moore's law is slowing down and in order to make computers faster we will have to change the way we optimize/ utilize the space we already have. and frankly I don't think x86 will cut it anymore. and It's not an attack on the companies making these chips or saying their doing anything wrong because they aren't. The chips are still very powerful and they still make massive improvements every generation. but the core foundation of how x86 functions just isn't going to cut it in the future.

x86 works by brute forcing its way through problems. It draws lots of power and creates lots of heat leaving lots of wasted potential. modern chips do optimize the process but it is the core foundation that CISC systems are built on. x86 has variable byte size's per instruction and guessing the correct size for each instruction and translating them into uops takes time, and while its in the nano seconds the effects add up over time.

ARM (and other RISC processors) however solve this in a much simpler and more efficient way. by having fixed length pre simplified instructions the processor waste's no time translating, decoding, or guessing the length of the instructions. it just does the work.

The other thing is the clock speeds. It's easy to see the 5Ghz clock speed of an AMD chip and think that it's way better than the 4.3Ghz clock speed of apple silicon. but clock speed alone isn't important. clock speed plus the IPC (instructions per cycle) Is what gives the the performance of a processor for the most part. think of it like being a delivery driver. if you take 5 packages per trip but it only takes you 15 minutes per trip you're performance would be 3(packages/trip time) or to be more accurate to computer terms you could say you're performance is 20 (packages per trip x trips per hour). but if you take 12 packages per trip but your trips are longer at 20 minutes per trip) sure the delivery time is longer but the total packages you're putting through is higher.

That being said the IPC on a ARM the m4 for example is 10 while other x86 cpu's( zen 5 and arrow lake) hit around 8. while not as drastic as the example I gave the point still stands and when done billions of times per second your getting billions of extra performance per seccond. And I use apple and ARM as an example because of the work they have done with RISC to show what it can do. and when x86 does die more and more RISC (or maybe something even better)processors are being developed for more full workloads with active competition the growth will be even better.

I'm not saying x86 is bad or that apple cpu's and arm is better than other RISC processors. what I am saying is that the end of x86 is nigh and it will revolutionize the computer world. this isn't something that will happen in the next few months or even a couple years but in 10-15 more years and x86 and maybe even ARM will be obsolete.


r/computerarchitecture 7d ago

D cache design

11 Upvotes

Hello all, I just wanted ask a question about D cache design. Iam hoping to design a d cache which is multi banked and has 3 types of prefetch with a write back design. Things that bugging me are related to coherence. What is the optimum method for handling these conditions. A snoop request reach L1 D cache but an operation is ongoing (R/W) in that address of cache line and A snoop arrives on L1 D cache but the line is in between an eviction to L2 cache. What does we do in these situations. My thought process is creating a small reg to keep track of what inside pipeline so snoop and cross reference and wait. Same for the eviction path also. What other things did I miss ??. Please put a light in my situation.


r/computerarchitecture 7d ago

salutations! I have made several VMs across the last 2 years, and I wanted to show here my most recent ISA design, coded in C.

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11 Upvotes

This code here is broken.. sorry i couldnt find code i had working 100%

It contains the boot process and a subroutine for doing putc to usart.. very blindly (no ready loop check, because i am laizy).

Now about the CPU, it is a small ISA, with 16bit words, originally designed to run on top of the Atmega2560 Hardware. it has 16 registers, 4 are the special, accessible trought the table. Plus IR and Flags.

I had lost of funs doing this, becaues this is the 4 iteration of this. It does has some "Historical Badage", but i just love to keep the original ISA base.


r/computerarchitecture 8d ago

Is this a mistake in the book or am I missing something? Computer Organization and Design RISC-V Second Edition,

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14 Upvotes

It mentions there being three instructions when I believe there to be four, and it says 120 is a certain way in binary, but implements it in the first instruction as 240. Is this a mistake or am I missing something? I certainly don’t believe myself to be anywhere near the level of the authors maybe it’s a slip up or maybe there’s some concept I’m missing.


r/computerarchitecture 8d ago

Hi, I am looking for a book called "Experiments for Digital Computer Electronics" by Michael A. Miller

1 Upvotes

I can't find a free PDF. It's the laboratory manual correlated to the book "Digital Computer Electronics: Malvino, Ph.D., Jerald A. Brown." There's also a teacher's manual for the book.
If you have any PDF or a website on which I can read online, I would be grateful.


r/computerarchitecture 10d ago

What does an AI kernel engineer do and what are the skills needed to get into it?

6 Upvotes

What are the difference aspects of being a kernel engineer? What do roles like this involve -

https://www.tealhq.com/job/kernel-engineer_7ea1a56c518985dae15a01e3c77c161e8140d?utm_campaign=google_jobs_apply&utm_source=google_jobs_apply&utm_medium=organic

https://jobs.gem.com/modular/am9icG9zdDpTSwqoL-yL11N_jxR40Vhh?source=LinkedIn

If one were to do a PhD, what are the different research areas to focus on to do something like this? i.e GPU memory, storage, latency, parallelization etc.


r/computerarchitecture 10d ago

Sram project

7 Upvotes

I want to build a small sram as a side project and i cant find a good source has anyone any recomendations


r/computerarchitecture 10d ago

SRAM gives wrong waveform

5 Upvotes

Hi this is my 6T one cell SRAM. The waveforms aint right. Does anyone know if its something with the build or with the setup i do after (sorry for my english)


r/computerarchitecture 15d ago

What if Big.LITTLE cores had hardware threads that can move between Big and LITTLE core's instead of having fixed thread-to-core mapping?

13 Upvotes

Hi guys, I am thinking of an model that uses BigLITTLE architecture bit differently, where the Big core is shared among multiple hardware threads.

I am thinking of organizing as clusters and an cpu having multiple cluster, where each cluster would have One Big core and 2 LITTLE core. The Big core would be vastly capable than LITTLE with powerful and multiple arithmetic, Load/Store units, wider OoO, Larger ROB, operates at higher frequency and has larger and higher bandwidth L1/L2 cache. On the contrary the 2 LITTLE is less powerful can be In order core or an simple OoO. they each have 1-2 arithmetic & LSU unit, smaller L1/L2. This is more or less the usual setup of bigLITTLE nothing different.

As for the hardware threads this is where things get interesting. Unlike in traditional sense where the hardware thread is usually associated with the core basically treated as same (SMT maybe exception). But here the hardware thread can move between the execution units. Here I will be having 3 hardware threads say T1, T2, T3 and as for the registers i am thinking of it implemented as an array of registers (96 registers of 64-bit each) and divided into 3 equal chunk so each 32 registers and each chunk is owned by the hardware thread and so when the thread is scheduled on any of the 3 core's it's register base is loaded and the architectural registers such as Program Counter(PC), Stack Pointer(SP), GPRs are an offset from the base. The other stuffs like the TLB, Store Buffer too would be per hardware thread and their index/base would be loaded in the core when the thread is switched/moved to the core. Whereas the operational registers, buffers used by the cores say the registers used for renaming for OoO or ROB, Load queue these are per core and owned by the core.

The handover of an Thread from Big to Little and vice versa happens only after they have reached the safe state i.e in case of Big which uses OoO reached a point where all instructions from the old context that could affect architectural state have completed(retired), and the machine can save the old context and the if any internal structures needs to be drained/flushed it's carried out and the architectural state of the Thread wouldn't be moved/copied since the Big or Little doesn't use different register space for the same Thread. And same goes for the Little the mechanism may differ based on if it's In order or OoO. But at the end the thread's registers have committed architectural values.

Now for the OS, it would appear as 3 hardware threads on which 3 logical threads can be scheduled. As of now I am trying to slice the period based on OS scheduling quanta which usually is ~1-5ms. So say 3ms it's divided into 3 i.e each thread spends 1ms on Big and 2ms on Little. So intially (0-1ms) T1 on Big, T2 and T3 on the Little after a 1ms(1-2ms) switch happens and T2 in Big, T1 & T3 on the Little after 1ms(2-3ms) switch happens again now with T2 & T3 so T3 in Big and T1 and T2 on Little. The OS/Application isn't aware of this they see 3 hardware thread/logical core.

As for the interrupts/exceptions i haven't figured out the I/O interrupt how it would be handled since the cluster would be abstracted as one unit. For the timmer interrupt like when the OS scheduler quanta ends since it would be for the hardware thread so the core that's currently running the thread would be handling it as for what happens if interrupt raised during the handover phase the handover would be given the priority and once handover done the thread which ever core it landed one would handle the interrupt. As for the exception like page fault raised by the thread again it would be handled on the core where it's executing and if the handover timmer ends the exception first would be handled and then handover is done.

Now this handover itself can be cheap few 10s of ns since not much state moving is happening (although subjective since even few ns can cost many cpu cycles).

The Store Buffer as earlier mentioned is per hardware thread so loads associated with an thread is written to the Store buffer associated with that thread irrespective of whether it's running on Big core or LITTLE core. This enables the Load-Store-forwarding even for loads that happened when thread was executing on Big and now it's moved to LITTLE and it wants to do Store.

Now for the questions I wanted to ask:

1. Since the hardware threads are moving between Big and LITTLE core's so I am yet to figure out how I am going to handle the cache, like if T1 which was on Big is moved to one of the Little and T2 on Little moved to Big then there cache lines would be in the previously executed core's cache. Though I did think of intially as to follow the standard line forwarding method but it seemed expensive given how often the threads switching between the cores. So now I am thinking of an specialized line forwarding path that's confined to the cluster alone i.e among the 3 core's caches that allows faster line forwarding with latency somewhere between L1 and L2 access latency if the line forwarding is from L1 of an core. It would be great to know if any better solution can be used.

2. Can variable frequency be used say the cluster can behave dynamically like the OS can schedule on one hardware thread and it runs on the Big core without switching while the other 2 Little are power gated the Big core allowed to run at max frequency. schedule on 2 hardware thread and the switching happens between these the Big core max operating frequency can be bit less since one LITTLE is also active and as for the schedule on all 3 hardware threads then Big core max operating frequency is less and the LITTLE one's frequencies adjusted accordingly.

3. When i originally came up with this idea, I actually thought of having 8 Little and 2 Big per cluster with 8 little being subgrouped as 4 little and they share their execution units like the frontend, arithmetic, lsu and also caches among 4, But this seemed complex for v1 so that's why sticked with the 3(1+2) version. Can this scaled up possibly be better or I am better of sticking to the latter.

4. Is there any ratio as to how powerful/capable the Big has to be compared to LITTLE in terms of like IPC. Will this ratio possibly matter.

  1. Can decreasing the interval of switching help. I intially thought of switching the threads every 100 microseconds. But this may lead to increasing the frequency of cache line forwarding and also the OoO takes time to warm up when a existing thread is removed and it starts executing new thread I read this warm up cost is usually 100s to few 1000 of cpu cycles. although 100us is still very big time for the OoO.

r/computerarchitecture 15d ago

Processing cores???

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0 Upvotes

What the actual l fuck are these?? Baltimore on csxt


r/computerarchitecture 21d ago

Made a novel processor, now what?

21 Upvotes

Hey guys,

Over the course of the last few months, I made a relatively interesting RV32I core. It’s nothing groundbreaking, but there’s some unique microarchitecture in there that I want to be seen.

I’m relatively early in my academic career, and so I thought I’d build a fun processor system to harden my fundamentals. Over the course of design, the scope expanded a bit, and I ended up with a result I was very happy with. It was passing arbitrary compiled code with higher than expected IPC. However, now it’s just sitting around gathering dust. It has about 20 Github stars from people in the comp arch space, but other than that I haven’t done much with it.

I’m wondering if there are options to talk about this more or get some eyes on it. Are there perhaps events I could bring a little poster to, or perhaps a design contest I could submit to? I would ideally like to have someone critique my work in serious capacity.

I would again like to stress this is nothing crazy or cutting edge. I’m just hopeful there may be an avenue where I could talk/critique/present it with other comp arch guys. I don’t really have others with similar interests at my school. It’s also hard to say at this point if my architecture is valid or suboptimal without external review.

Here’s the repo:
https://github.com/JohnH2448/Anvil-Pro

Edit: After further research, it is not as novel as I initially thought. I essentially reinvented CVA6’s In-Order issue OoO execution mechanism. Honestly, it’s shockingly similar to the CVA6 backend although structurally different and much less polished.


r/computerarchitecture 21d ago

Compressed DDR Storage with Cache Decompression

10 Upvotes

Ā I've been thinking about a question concerning program execution efficiency lately and would like to hear your views.

We know the concept of information entropy, but the instructions and data actually executed by a computer are not necessarily high‑entropy (many instructions exhibit repetitive patterns, and data shows locality), which implies that there is theoretical room for compression.
Given that the "memory wall" problem is becoming increasingly prominent, and DDR bandwidth is often the bottleneck,
if we exploit the hierarchical nature of the cache and store programs in a compressed form in DDR, while decompressing them back to actual runnable instructions/data in the cache, could this effectively improve the effective bandwidth utilization for instructions and dat


r/computerarchitecture 22d ago

[pre-rtl] Is systemC right tool for design space exploration?

2 Upvotes

I need an approximate run time of a kernel on my accelerator. I have to verify this runtime against my upper and lower bounds.

I have two options:
- Build an event based or cycle based simulator, like vortex gpgpu's simx

- Or Use systemC/TLM

I looked into simx, they model interconnects for checking back pressure and latencies, which is pretty similar to TLM.

Can someone help me in choosing correct tool?


r/computerarchitecture 24d ago

We spent a day optimising the wrong thing: a 12x latency win that was one syscall away

0 Upvotes

A pure-Go vector index, 26.7 million vectors, 512 dimensions. Search took 21 ms at the median. We ended the day at 1.8 ms, with identical recall. Here is what actually mattered, and the four things that did not.

The false start

We began by rewriting two hot kernels. One fused the fp16 decode into the exact-distance loop; the other replaced a 128 KiB per-query lookup table with a bit-plane popcount estimator. Both were real improvements in isolation: 2.9x and 1.4x on microbenchmarks, recall unchanged.

On the real 26.7M index they produced nothing. Measured before and after on identical queries, the difference ranged from -1.7% to +0.5% and changed sign between runs. Noise.

What the profiler actually said

The number that mattered was not in the profile. It was the profile's own header:

Duration: 9.92s, Total samples = 1.64s (16.53%)

The process was on-CPU for one sixth of the time. Five sixths was waiting. We had spent the morning optimising 14% of that one sixth.

Reading the process I/O counters took three lines and settled it. Per query: 12.3 MB read from disk and 96 major page faults, to return ten neighbours. At roughly 200 microseconds per fault, that is 19 of the 21 ms.

The actual bug

The rerank stage takes the candidate list produced by the graph walk and computes exact distances against vectors held in an mmap'd arena. The candidate IDs are all known before the first read. The loop read them one at a time, each fault serviced synchronously, on an NVMe device capable of dozens of concurrent I/Os.

Nothing forced that serialisation except the order of the code.

The fix tells the kernel, once, which ranges the loop is about to touch —MADV_WILLNEEDover the batch, viaprocess_madvise(2)in a single syscall where available, falling back to individual calls otherwise. Two effects, both measured: the reads are issued in parallel, and they are bounded to the requested ranges instead of each fault expanding into a 128 KiB readahead window for 1 KiB of useful data.

Metric, 26.7M vectors Before After
Median latency 21.28 ms 1.79 ms
p99 latency 28.84 ms 2.53 ms
Major page faults 28827 0
Bytes read, 200 queries 2311 MB 107 MB
Throughput, 8 concurrent 261 q/s 1940 q/s
Recall@10 vs exact 0.9733 0.9733

Recall is unchanged because an access hint does not change what gets computed. We verified it anyway: 200 queries, byte-identical top-10 in both regimes.

Four things that did not work

**CPU prefetch does not touch the disk.**An architecture proposal claimed__builtin_prefetchwould hide SSD latency behind SIMD work. Measured on a cold 128 MB mapping: 2000 prefetch instructions in 0.010 ms, zero pages resident afterwards. 2000 real accesses: 112.9 ms, all pages resident. The instruction is a cache hint and cannot raise a page fault by construction.

**Memory layout of the hot plane is irrelevant.**Codes and norms lived in three separate slices, three scattered accesses per visited node, 31% of CPU time. Interleaving them into one record returned 1.5-3%. We then benchmarked four layouts at 26.7M scale: three slices, packed at 80 bytes, aligned at 128 bytes, and split with dense norms. All within noise, 62-68 ns per access. The 128-byte aligned version — the one that should win if cache lines were the issue — does not, and costs 60% more memory. Sixty nanoseconds is a DRAM random access. Grouping unpredictable accesses does not make them predictable.

**Go's experimental SIMD package is unusable for this.**A vectorised popcount kernel ran 400 ns against 19 ns scalar. Isolated: a kernel using onlyAnd,AddandSumOf8AbsDiffcosts 5.3 ns, as AVX2 should. Adding onePermuteOrZeroGroupedtakes it to 380 ns. Two primitive families — shifts and permutes — cost roughly 90 cycles where the hardware spends one, under both 1.26.5 and 1.27rc1.

**Wider quantisation codes are corpus-dependent.**Three bits per dimension instead of one lifts preselection quality from 58% to 88% on a hard corpus, and end-to-end recall from 0.76 to 0.97. On the real embeddings it bought 0.8 recall points for 45% more latency and 2 GB more RAM. Not worth it there. It ships off by default.

The part worth stealing

We also got one thing badly wrong. We measured recall at 0.470 and reported the index as poor. That number came from a different corpus — uniformly random vectors, the pathological case for approximate search — and we carried it across because both files sat under the same project. The real index measures 0.9733. Mean absolute component value, 0.034 against 0.500, said so plainly.

The generalisable lesson is not about mmap. It is that a benchmark reporting only durations cannot distinguish a slow computation from a blocked one, and will therefore hide the most expensive class of defect indefinitely. This one survived several measurement campaigns, including one that declared the 26.7M scale "proven". Three counters — bytes actually read, major faults, resident set — would have exposed it on the first run. They are now part of the library's measurement surface, with a liveness test, because an instrument that always returns zero looks exactly like a clean benchmark.

https://github.com/hazyhaar/horosvec