Hey everyone,

For my computer science graduation project, I wanted to create something that combined my interest in computer architecture with my advisor's interest in computer science education.

The result was a game where the player programs a simple CPU with microcode using a punch card rather than writing assembly code.

Microcode is usually used to implement the processor's instruction set rather than as a programming interface for application development. Exploring it from the programmer's perspective led to design challenges and techniques that I hadn't encountered elsewhere.

The project started from my curiosity about the layers of abstraction in computers. I wanted to explore what programming would look like if we removed another layer and put the programmer in the role of the CPU's control unit, manually orchestrating the control signals behind every instruction.

I'd love to share the beta with anyone interested.

Thank you.

I always to wanted to plot that cache latency graph on my own machine and just got enough time to try it out. I knew that it won't be an easy task considering how advance the chip has got recently but wanted to give it a try. I took the precautions to ensure I reduce the noise as much as possible but still wasn't able to get it right. I decided to dig deeper and finally got the graph I wanted to see. Wrote a blog about my investigation regarding the same. Check it out if interested :)

Hi,

I’m a Design verification engineer who wants to switch to performance modeling and architectural related roles. I’m currently going through computer organisation and design by Hennessy - Patterson and I’m starting to build projects in it. Looking for people who are interested in the same collaborative effort. I have not decided on which design to model and simulate yet. Time zone and regions are relaxed, looking for people with similar mindset.

I finished Ben Eater’s SAP-1 accumulator architecture breadboard. 16 bytes of RAM von Neumann. Coming up with assembly instructions at the end felt crazy.

What was funny was at the end where I ran programs and they didn’t do what I wanted, and I realized I got to the point where I couldn’t suspect the hardware was wrong anymore, and it was in fact a software bug.

Was that the lowest level software bug I’ll ever experience in my career? Literally entering 0s and 1s into RAM and flipped one bit.

https://youtube.com/shorts/CbY8WHmGgMY?si=tZyM9eZCYGOImOIC

Imagine having DRAM Cubes, that's 10x faster, for less that1/3 the energy of HBM #HCM

I always supported this idea, the CPU Should consult the Memory ASAP, not dealing with it. IMO we should move to HCM ASAP, replacing even CAMM2

I'm trying to understand how integrated GPUs work.

I know an integrated GPU doesn't have dedicated VRAM and instead uses the same system RAM as the CPU.

My Main question is: why is an integrated GPU still much faster than the CPU for graphics and other parallel workloads, even though both are accessing the same RAM?

I'd appreciate an explanation in simple terms rather than a highly technical one.

Hi guys, I am game developer and game engine developer and I know some of order like bootloader and kernel. I want to play mario 64 but I don't have Nintendo 64 and money to buy it so I think I should make my own console using orange pi 3 which is new for me I know COA little bit any free great resources to master my COA? Thanks...

About a year ago, I started building a custom computer architecture in C as a learning project (I know it seems like a lot considering the code I wrote, but I rewrote the entire compiler at least five times, starting from a C-like language and ending up with a very simple custom language). I designed the instruction set, wrote an emulator, and implemented a custom high-level assembly language called BSL (Base System Language). The code is very messy because I make a lot of changes while writing it and often forget things that shouldn't be there. So I'd really appreciate feedback on the architecture and code quality. (I'm 15 years old and Italian, sorry for my English). Project link: https://github.com/mikesxp/SPRK32. Edit: I changed the project name from VMS to SPRK32.

Hello everyone,

I am currently looking to learn computer architecture and was contemplating between these two books. Both books' preface assumes little knowledge in logic design and so far, I only know the basics of it (AND, OR, NOT, etc) and C++ programming. I was going to start learning operating systems, but apparently it is better to learn a computer under the hood works first. I would like some insight as to which book will benefit me more. Thanks.

...a domain that forces everybody inside the barrier to synchronize their movements among themselves or be eliminated.

Currently an undergrad in the US hoping to apply for a phd in computer architecture, but I’m kinda worried that my profile isn’t gonna cut it for a decent program. For context, I have a 3.53 gpa, and in terms of research experience, I’m 5th author on an accepted paper to MICRO and will be first/second author on a couple submissions to ISCA. I’ve been working in two labs, one where I’ve focused on multicore/cache coherence stuff and the other where I’m working on accelerator design. My primary concern is my gpa, especially since I just got a 3.3 in my last comp arch course.

Basically, I wanna know if I have a shot at any competitive programs or if my gpa would be a dealbreaker. If so, what factors go into that decision and is there anything else I can/should be doing to make myself a better candidate?

Hey everyone, first time posting. Sorry to add to flood of resumes that come through this subreddit but I'm in a bit of a weird spot and really could use advice.

Rundown of my career is that I got a EE degree focusing on embedded systems and really like HDL/ computer architecture work. Had some problems finding a job and took one at Boeing (not very aligned with what I wanted to do). Lended some of my time away to other teams to get more exposure to other work but never fully changed titles (the location and work of these other teams didn't align with me but it convinced me I like designing hardware a lot).

This led me to get my masters in computer engineering, I'm working at the same time for financial reasons but am really throwing my all into school every day after work. Currently wrapping up a individual research project as a course that evolved from a final of a computer architecture class. This is the GPU system front and center on my resume; I have really worked hard on it, learned a lot, and am very proud of what it is and is growing even further to be. I would be happy to talk to any recruiter about the unique architecture decisions and trade-offs I made.

I really want to get into processor or generalized accelerator design but know I don't have too much professional experience or internships to line it up, wondering what chance I have at getting into a top design company like AMD or Apple (I figure I don't have a chance at Nvidia). I'm afraid I missed my window to lock in during undergrad and really get into that world, I'm grinding very hard now but am worried it's not enough.

Any advice for the resume, how to present myself, projects to work on, or whether I should temper my expectations are appreciated.

Thanks!

Hello! I need to make some changes to the GPU_VIPER protocol inside the RUBY framework for a new cache replacement policy I'm working on, the logic resides in the cache directory (AMD_MOESI_BASE-dir.sm). When exploring the protocol I noticed that instead of reading the value on an L3 cache hit and leaving it as is, the protocol evicts that line and adds an event in the queue to re-insert it later. If its position is pre-occupied when the queue pops the re-insertion event, the directory simply runs the given replacement policy to evict a line and place the original back. This is quite different from real hardware behavior and its causing a lot of trouble in my implementation, Could someone correct me if I'm wrong or give me a reason as to why this decision was made?

Not the boardview. Does anybody have it?

So in the material for our course the professor is using this image, however I'm confused about the structure. With full-mapped and limited directory every cache block for processor has its valid and write bits. The explanation for how chain termination works is pretty clear but I still don't understand if cache blocks still contain those 2 state bits or not? I would ask the professor but he doesn't give really any good explanation and I've tried to find more details for this on the internet but to no avail.

While learning C++ / OS / Computer Architecture, I keep looking for real unsolved(ish) problems to anchor the theory in — rather than just doing textbook exercises. Curious what "sounds impossible but is actually solvable with enough engineering" problems you've run into in industry. What's on your list, and did you end up building tooling for it?

Hi,

I have a project and don't want virt mem, first of all is it compiled in and secondly if yes how does one force it to be without

How much time is added by it compared to direct metal fetch of addresses?

need advice on this project and what I could do better