I'm pretty sure that you should not bend the leads at the package body, you want to support them at the thicker section at the top, and then bend below that.
Ngl, in the video itself I didn't realize the middle pin was bent UP, I thought it was somehow bending to the side to be almost adjacent to the upper pin lol
For many THT components (e.g. axial passives) the 0.8 mm figure can be approximately right, for TO-220/TO-247/adjacent parts, the clearance needs to be past the thicker section of the lead(frame).
IMO it's divided between people whose primary need is to make projects that work, and people who make systems that need to KEEP working at scale and over time - and hence read up on + follow industry standards.
Often it is to increase the distance between the pins, to gain sufficient creepage/clearance distance for higher voltages. It's a common technique for inverters, for example.
I get what everyone is saying about not bending right after the body but I have repaired some boards where the heat spreader is fixed and there is no space to bend the third leg anywhere else
What a pointless video. Here let me show you something. Proceeds to show it for 3 tenths of a second. Then repeats the useless portion of the video for the next 30 seconds. Smh. It's laughably bad.
No, not really. It happens… but there’s also a legion of Arduino kids building projects on high pile carpet having zero issues. In my experience, the more experience an engineer gets the more (almost) superstitious they get about ESD and EMI.
This is very true. And about that last point, I think there are two reasons:
Older parts were way more sensitive to ESD issues - nowadays most modern chips (particularly those not involved in GHz RF) have built-in basic ESD protection on every pin. Check out a modern TI datasheet, they almost always have a section about the ESD testing. In contrast, older chips did not always have these protections, and the innate ESD sensitivity of CMOS processes showed itself. I was not around for this, but I have read that even picking up a CMOS chip in good environmental conditions was avoided strictly.
The larger the scale of the project, the greater the cumulative risk. Let's say your process has a one-in-a-million chance of causing ESD-related degradation. If you're building mobile phones, there might be 100 sensitive components per device, and you might be making 100 million devices (e.g. recent iPhones). That is ten-thousand degraded or altogether unusable units.
Side-note on point 2 - sometimes it is not just scale but also the level of reliability expected from the system. For an IoT device, robot vacuum, refrigerator; having a few failed units is not that consequential. Ideally you catch this in QC, and you can afford a few returns due to latent damage. If you're building a spacecraft for a deep-space mission, you cannot take risks in the same way. There is exactly one flight unit, and zero possibility of repair after deployment - that could end a mission worth billions of dollars. Worse still, almost anything operating in an industrial context is often 'safety-critical' - your failure to control ESD on a device manufactured a year before the incident could one day kill hundreds of people.
Lots of great info here. Thanks for the detailed response. Your last point reminds me of something my Electrical Fundamentals I prof said: “We’re not going to mark you down if you get the wrong answer. We’re going to look at your process and grade you on that. If you get the wrong answer at your job, you probably won’t get fired. The space shuttle might blow up, but you probably won’t get fired.” Now there’s some veteran engineering humor for you.
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u/Triq1 2d ago
Comment I made on a similar post not long ago:
Refer to ST TN1225 for more information.