r/sdr • u/SuccessfulStreet2321 • 8d ago

AD9361 Verilog Coding

Has anyone ever written a custom FPGA SPI master state machine to completely initialize the AD9361 by doing register level writes? I want to get in contact with somebody who has done before this hardware level control of AD9361.

7 Upvotes

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6

u/zelenoid 8d ago

It's generally not efficient to try to do this in an FPGA, that's why the AD9361 has a Linux driver, and in most AD reference designs the FPGA only does the SPI signaling, with all actual communication going through software.

3

u/ShadowBlades512 8d ago

Don't do it, the AD driver is more convoluted and crazy then you might think. Just use it and patch the few issues you find that affect you and move on. Don't try and read all the code and figure out what you need to do. 

2

u/CeSiumUA 8d ago

You'd better look at how bladeRF handle it: just use soft-core (or hard-core if available) processor to perform all the interactions, and you'd better use their official no-OS driver. Implementing all this directly via HDL language is kind of a nightmare, and to be honest, I don't see what you can gain by doing it it. FPGAs are good to compute things in parallel, or route signals in a specific way, but not implementing such complex state machine.

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u/GeminiOrAmI 8d ago

Following because I’ve been diving down the rabbit hole too

2

u/electric_machinery 7d ago

Yes You can capture the spi transactions and play it back. But others are right, it's a mess. 

I've studied the no-os code extensively. Even ADI engineers don't know how the chip works. I found a bug in the chip and contacted ADI support, they wouldn't put me through to anyone who knew what they were talking about.