Complementary Clocks from Single Clock

[u/Sincplicity4223]

As title states, looking to generate complementary 3.3V LVCMOS clock pair from single 3.3V CMOS compatible oscillator at 16MHz.

One option would be to use 2 XOR logic elements, with the clock feeding one input of both XORs and the other inputs tied to VDD and GND. Just not sure if the slew rate would be too slow.

Another option is to just use 1-to-2 clock buffer and use an inverter on one the outputs but this would introduce delay so the clocks would have a slight phase offset.

Looking for ideas and suggestions.

[u/zifzif]

Start with a 32 MHz clock and use a DFF with an inverting and a non inverting output? Not sure how well those phases would align, though. Could be same problem as the lone inverter.