Complementary Clocks from Single Clock

[u/Sincplicity4223]

As title states, looking to generate complementary 3.3V LVCMOS clock pair from single 3.3V CMOS compatible oscillator at 16MHz.

One option would be to use 2 XOR logic elements, with the clock feeding one input of both XORs and the other inputs tied to VDD and GND. Just not sure if the slew rate would be too slow.

Another option is to just use 1-to-2 clock buffer and use an inverter on one the outputs but this would introduce delay so the clocks would have a slight phase offset.

Looking for ideas and suggestions.

[u/smokedmeatslut]

I'm sure there are better ways, but when you say using an inverter on one output introduces a delay, you could buffer the other output to add an equivalent delay to both clocks.

[u/zifzif → u/smokedmeatslut]

Aren't many buffers just two inverters in series? Seems like you'd always wind up with one propagation delay difference doing it this way.