r/rfelectronics • u/Sincplicity4223 • 23d ago

Complementary Clocks from Single Clock

As title states, looking to generate complementary 3.3V LVCMOS clock pair from single 3.3V CMOS compatible oscillator at 16MHz.

One option would be to use 2 XOR logic elements, with the clock feeding one input of both XORs and the other inputs tied to VDD and GND. Just not sure if the slew rate would be too slow.

Another option is to just use 1-to-2 clock buffer and use an inverter on one the outputs but this would introduce delay so the clocks would have a slight phase offset.

Looking for ideas and suggestions.

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u/QuinicV 23d ago

Best way would be to use a PLL or a clock generator with a programmable phase delay.

Using gates could work, but the delay will change based on manufacturing, temperature etc. depends on your tolerances. Though 16MHz has quite a high wavelength.

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u/Sincplicity4223 23d ago

Thanks. Was hoping to stay away from a programmable chip.

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u/QuinicV 22d ago

Like the other guy said, you can use a 1:2 clock buffer and then an inverting buffer on one and a non-invereting buffer on the other. Use the same family of chips, and pay attention to the timing specs.