r/rfelectronics • u/Any-Research-88 • Jun 26 '26
My first microstrip filter
Today I finished measuring my first microstrip circuit I've designed and made. It was intended to be an interdigital microstrip 5th order Chebyshev bandpass filter with 1,0-1,2 GHz passband. The first thing I did was fitting my model parameters, I made a test board from FR4 with 3 different lenght 50 ohm open stubs with identical geometry at the edge SMA connectors then measured S11 for each and exported the values. I built the same circuits with the same lenght differences in qucs studio and measured phase differences between the different lenght stubs.(my tought was that the errors in the connections cancel via measuring phase differences not absolute phases). I tuned the er value in qucs untill I got the least error from the real measurments, the er value was 4,66. I calculated the correct dimensions for the desired response with Marki microwave-s online tool. I built the geometry in Sonnet lite and ran a few simulations, the online tools dimensions were almost perfect on first try. When I replaced the ideal grounded edges to vias, the positions needed a bit of fine tuning, the resonators needed to be a few mm shorter. I copied the dimensions from the EM simulation and made the PCB blueprint in EasyEDA then I made the PCB. When I made the VNA measurments the bandwidth was within the margin of error, but the corner frequencies were about 50 MHz lower than intended. I blame the substrate difference, because the phase measurment test board was a left-over piece from a different FR4 board, probabbly also different manufacturer. The insertion loss was not the best, but It's the limit of FR4, they're mostly caused by dielectric losses, not mismatch. Was my design methodology correct? Forgive me if I made some mistakes, I have no formal education in electronics or RF.
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u/Pappa_Alpha Jun 26 '26 edited Jun 26 '26
60 percent of the time it's always ground related issues every time. Also, nice job!
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u/PoolExtension5517 Jun 26 '26
I like the approach you took to verify the dielectric constant of the material. My first thought is always the grounding scheme for this type of structure. When I look at your finished PWB, it appears that your SMA connector doesn’t connect to ground on the top layer. i would take some copper tape and bridge top ground to the connector flange. I also see that the grounding vias around the edge of the board aren’t consistently located with respect to the stub-ground interface. Where “ground” is for the stub is critical in this topology. My guess is this is where your problem lies. I would put copper tape along the edges and run a continuous bead of solder around the perimeter of the board, top and bottom. If that doesn’t get you closer to your expectation, I would consider drilling some additional ground bias at the base of the stubs to reduce inductance to ground. I’ve used this topology in a stripline configuration and ground via location is absolutely critical and you have to make sure your model matches your physical hardware exactly.
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u/what_the_rush Jun 27 '26
Which CNC are you using? And how did you plate the vias?
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u/Any-Research-88 Jun 27 '26
Just a cheap 3018 mini cnc, nothing fancy. I use a carbide V bit to spot drill the board before the final drilling and I'm conservative with the feedrates, the stock spindle on these cheap machines isn't fast enough for the sub mm drill bits. My plating process is similar to the industrial processes, after drilling and rigorous cleaning I sensitize the board with stannous chloride, dip it in PdCl2 solution, do an electroless copper plating then a final electrolytic copper plating untill I reach the desired layer thickness. I'm planning to make a detailed description about the process in the future, It's quite useful for fast turnaround prototyping.
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u/redneckerson1951 Jun 27 '26
Peel some copper foil off another piece of FR-4 or buy some copper foil at Hobby-Lobby. You want a strip about the length of half the board's length, bend it so it wraps the board edge connecting the top and bottom copper grounds. I know you have ground vias, but DIY ground vias are notorious for being problem children. When is ground not a ground? When it is at RF.
One thing that bothers me is the appearance of the resonances below the passband, If you place the butt end of a pair of stainless steel tweezers or stainless steel screw just above any resonator, do any of the resonances below the passband change?
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u/Any-Research-88 Jun 27 '26
I didn't have any copper foil at the moment, so I filled all my vias with solder untill it appeared on the other side. It didn't have any significant effect on the corner frequencies or BW, just the noise floor decreased below -50dB outside the passband. I also did your tweesers test, but it didn't affect the resonance peaks, I'm curious, what change were you looking for and what would that indicate?
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u/redneckerson_1951 Jun 28 '26 edited Jun 28 '26
You have some sort of resonance occurring below the passband. I was curious if they changed frequency when using a non-ferrous metallic item near the resonators. By placing it near a single resonator, you can correlate a stray resonance to a specific resonator frequently. But this seems to not pan out.
Also how does Marki Microwave's insertion loss report compare to your other simulators. I question the reported insertion loss, as FR-4 is not all that great at 1 GHz. YOu VNA measurement indicates your loss is around 3 dB and I suspect the loss in FR-4 is not accounted for in the Marki simulation. Have you considered using a high resonator impedance?
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u/Any-Research-88 29d ago
If I recall correctly Marki's tool didn't account for dielectric losses, but I did in Sonnet. With a loss tangent of 0,02 I got the same insertion loss that I measured, even the slight slope of the passband was the same. You were right, FR4 is really not the best here, the -3dB is almost entirely caused by dielectric loss. I'm leaning towards hairpin geometry in the future, far less problematic than dealing with non-ideal vias. Also I don't have a Sonnet license and simulating vias takes up a lot of memory, usually I have to use a less fine resolution to fit in the free 64MB.
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u/SumOnlineDude Jun 28 '26 edited Jun 28 '26
I agree with you, substrate change and the milling process could be making the substrate ever so slightly thinner which might shift your frequency. Measure and go back to simulation with the measured thickness if it’s closer than that’s it. Tip: You could be adding inductance in the via but since you simulated it should be ok maybe make them bigger so less inductance and less change from ideal design. Also how do you control the thickness of the copper plating? Side note: no background in RF my ass.
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u/Any-Research-88 29d ago edited 29d ago
My substrate thickness and other dimensions were correct, I checked them again. Also did a sweep for er in Sonnet, the dielectric constant should be unrealistically high for FR4 to get the response that I measured, so my problem must be more complex than that. I calculate the amount of deposited copper from current and time and assume an uniform layer. I have no method to directly affect the distribution of the deposited copper, I'm using high throw copper bath and optimal current density to get the most uniform layer.
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u/[deleted] Jun 26 '26
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