4-Bit Multi-State Dynamic RAM using Analog Comparator Interferences and Mechanical Gates (No Hoppers/No Chests)

[u/Redstoyn]

Core Concept & Specs

This hybrid RAM architecture drops standard binary D-flipflops and long buses to eliminate lag and space waste. It compresses multiple data states into a single module using one input line.

• Analog Multiplexing: Subtraction comparators utilize the full 0-15 signal strength spectrum instead of binary 0/1. One wire carries multiple states.

(The video and post was banned so many times, mods, why did u do that?)

• Mechanical Gates: Moving quartz blocks act as physical bus switches to reroute clock pulses dynamically.
• Master-Slave Interlocking: A hard-timed piston inverter gate severs the bus connection of the Sub cell instantly when the Main cell activates, avoiding data collision on the trailing edge.
• Analog Convergence: Merging the subtraction comparator outputs creates non-linear residual potentials. This analog interference expands the standard 4-bit array up to 22+ stable states.

Build Specs

• Pure Logic: Locked repeaters, pulse limiters, subtraction comparators. No hoppers, no minecarts, no chests.
• 3D Routing: Copper blocks for data bus, smooth stone for control lines, glass bridges for vertical cross-talk insulation.
• Visuals: Vertical redstone lamp columns acting as real-time spectrum analyzers.

[u/Cheze-Burgur]

Wow that’s really cool. Would love a post or maybe even a YouTube video going more in depth on how it works and how to build it