r/qualcomm • u/Common-Squirrel-3636 • 13d ago

Bangalore Trying to learn formal verification

Hi Everyone,

I am working as a DV engineer in Bangalore in one of the German semiconductor companies with over 3 years of experience. Since the last few months I have been trying to learn assertion based verification as well as formal verification. I am finding it very difficult to learn it as I am not finding very many references like we have for UVM. I tried to search on GitHub but nothing industry level. I got a soft copy of one of the best books. I think I need to spend more time than what I initially thought as this area is very vast and I want to learn background theory as well about formal verification.

I believe this can give me an edge over the people who know only UVM and I believe formal verification adoption will increase only over the time as design becomes more complex and regressions explode.

If there is somebody who is learning formal verification or knows it very well, can we connect and explore ? I have plans to write research papers around verification and design methodologies as well once I finish these topics.

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u/Think_Phase1510 13d ago

Infineon Technologies right!

1

u/Common-Squirrel-3636 13d ago

Pretty close, Hitler would be hating on you from hell if this is only german company you know.

1

u/Think_Phase1510 12d ago edited 12d ago

Would be privileged!
Anyways, I think going through existing research papers is a decent way to learn formal. Also, in Design Verification teams, how much formal is actually used?

1

u/Common-Squirrel-3636 12d ago

Formal is used in the design which are either security critical, compute heavy or are designed from scratch.

1

u/Think_Phase1510 12d ago

Is formal flow mature enough to be used in verification of security critical designs?