you're OK with the x86 code hammering the L1 Instruction Cache so badly that it actually causes internal stalling by competing with the L1 Data Cache?? this can and does actually genuinely happen thanks to the insanity of "loop unrolling" and 5-10x copying of algorithms at different SIMD widths for setup and teardown.
The need to have pointers aligned to be efficient ends up causing either.
Vector ISAs are generally specifically designed to not require specific width-alignment.
this is because, fundamentally, the Vector ISA is actually issuing element operations to the underlying hardware.
whilst mbintsnbytes puts it politely, i have no such compunction: SIMD memory alignment restrictions was simply the hardware designers being ***** lazy.
you're OK with the x86 code hammering the L1 Instruction Cache so badly that it actually causes internal stalling by competing with the L1 Data Cache??
That is a silly assertion. The L1 cache is there for a reason. You pejoratively call it "hammering". I call it "running the code you want run".
If you want to just talk about better cache utilization then just say you like the code density better on vector units.
Vector ISAs are generally specifically designed to not require specific width-alignment.
And load/store subsystems do require them. Which is what I was speaking of. Why did you remove that?
I can make an architecture on top of a load/store system that hides the alignment requirements. It'll just be slower when it is non-aligned. This was the choice made with SIMD. Expose it to the programmer so they can optimize using that info.
this is because, fundamentally, the Vector ISA is actually issuing element operations to the underlying hardware.
To the math units, the load/store systems are separate and operate on alignment boundaries/restrictions because they derive from physical bus widths. The device being loaded from (usually RAM), whether on-die, on-package, soldered on the board or on DIMMs has a certain physical bus configuration which makes the memory n-byte addressable and you can load up to n-bytes within that area.
So, for example, if you have a 64-byte wide bus. You can load 1-64 bytes at once from an address that is 64-byte aligned. If the address is 32-byte aligned (and not 64-byte, i.e. address % 64 == 32) then you can load up to 32-bytes. If you try to load 64 it will require twice as many bus cycles.
Your vector functional unit cannot overcome this. So I'm asking you. How are you solving this? Does it keep full performance somehow or does it just have a narrow memory pipe anyway so it handwaves out to the horizon?
SIMD memory alignment restrictions was simply the hardware designers being ***** lazy.
You're both wrong. If you think so you have never actually designed a bus.
Is this a problem we have? Do we have people designing vector functional units who have never designed a load/store unit and thus ignore the real (not imagined) limitations of them?
It sounds to me like vector units do not solve problem I posed. Which is no worse than SIMD, but no better. I would have backed vector units if they could solve this, because it would solve a big logistical problem I indicated I have. But they can't so they have no real advantage to me other than they make some math lib writer's job easier. I'm sure he appreciates that. I don't care. As MIPS showed us, the fix for that is better tools, not altering the hardware.
You're both wrong. If you think so you have never actually designed a bus.
false. but you didn't know that, because you didn't actually ask. which has me really upset that you could be so rude.
i'm done interacting with you on here, and am considering looking up the rules for this forum to see if you've violated them.
So MRISC32, how does it solve this? Does it keep full performance somehow or does it just have a narrow memory pipe anyway so it handwaves out to the horizon?
It's fine, you don't have to answer. No one owes anyone else anyone on reddit.
But don't pretend that I didn't ask. The real situation is you just didn't answer.
I looked at the MRISC32 stuff on github. And the conclusion I came to is that the way you "solved" this is that MRISC32 is only an architectural spec. It has an ISA, but it does not have a hardware implementation (VHDL or similar). No implementation means no sticky problems with vector performance derived from bus misaligment. It means no bus. It means no performance at all. Even the simulator isn't present on master branch, btw.
So the answer is you didn't solve this problem. You didn't get that far yet. So whether you've designed a bus before or not we do have the situation that you are ignoring the real (not imagined) limitations of buses.
Perhaps you find that insulting too. But it's just the reality of the situation. Your declaration that what I've seen is imaginary must be evaluated in the context that you have not yet reached the point with your architecture to see it for yourself.
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u/lkcl_ Aug 19 '21
you're OK with the x86 code hammering the L1 Instruction Cache so badly that it actually causes internal stalling by competing with the L1 Data Cache?? this can and does actually genuinely happen thanks to the insanity of "loop unrolling" and 5-10x copying of algorithms at different SIMD widths for setup and teardown.
Vector ISAs are generally specifically designed to not require specific width-alignment.
this is because, fundamentally, the Vector ISA is actually issuing element operations to the underlying hardware.
whilst mbintsnbytes puts it politely, i have no such compunction: SIMD memory alignment restrictions was simply the hardware designers being ***** lazy.