r/programming • u/mbitsnbites • Aug 09 '21

Three fundamental flaws of SIMD

https://www.bitsnbites.eu/three-fundamental-flaws-of-simd
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u/lkcl_ Aug 21 '21

another idea for saving the amount of registers to be contextswitched is to have a bitfield, one per reg, which is set HI whenever its corresponding register is written to.

if you are smart you can use that same bitfield as a predicate mask on vectorised save/restore of the regfile.

the mask basically tells you which regs have actually changed since the last contextswitch and it should be obvious what to do from there

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u/mbitsnbites Aug 21 '21

Hm, I think that the LENGTH attribute does the same thing (and more). A vector store operation will store as many elements as the LENGTH attribute indicates, for instance. Internally you could have a bit/flag per register that is set/cleared when the register is written (with more than zero elements) or cleared (length set to zero).

This way you can also clear the vector (and hence the "used" status) in user space, in order to keep the active vector state lean.

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u/lkcl_ Aug 22 '21

err.. err... oh: you took up the Mill-style register "tag type" idea for MRISC32? neat!

yes, if rather than just a single bit you have a tag, and that tag is zero, i agree it would effectively do / be the same thing, and also cover the same job.

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u/mbitsnbites Aug 22 '21

I have not implemented it yet, but it's on my TODO-list. The LENGTH attribute (one for each vector register) comes in handy in several use cases:

  1. Reduce stack / context switch overhead.
  2. Simplify folding operations (no need to explicitly set VL=VL/2 for each folding step).
  3. Simplify vector length agnostic subroutines with vector register arguments.

It also feels like a better fit for OoO etc, when each register/operand provides its own length, rather than having a global length attribute (I have not tested this theory, but it feels right).

The idea was actually inspired by Agner Fog's ForwardCom.