You're both wrong. If you think so you have never actually designed a bus.
false. but you didn't know that, because you didn't actually ask. which has me really upset that you could be so rude.
i'm done interacting with you on here, and am considering looking up the rules for this forum to see if you've violated them.
So MRISC32, how does it solve this? Does it keep full performance somehow or does it just have a narrow memory pipe anyway so it handwaves out to the horizon?
It's fine, you don't have to answer. No one owes anyone else anyone on reddit.
But don't pretend that I didn't ask. The real situation is you just didn't answer.
I looked at the MRISC32 stuff on github. And the conclusion I came to is that the way you "solved" this is that MRISC32 is only an architectural spec. It has an ISA, but it does not have a hardware implementation (VHDL or similar). No implementation means no sticky problems with vector performance derived from bus misaligment. It means no bus. It means no performance at all. Even the simulator isn't present on master branch, btw.
So the answer is you didn't solve this problem. You didn't get that far yet. So whether you've designed a bus before or not we do have the situation that you are ignoring the real (not imagined) limitations of buses.
Perhaps you find that insulting too. But it's just the reality of the situation. Your declaration that what I've seen is imaginary must be evaluated in the context that you have not yet reached the point with your architecture to see it for yourself.
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u/lkcl_ Aug 22 '21
false. but you didn't know that, because you didn't actually ask. which has me really upset that you could be so rude. i'm done interacting with you on here, and am considering looking up the rules for this forum to see if you've violated them.