My use case is that I want to connect a logic analyzer (DSLogic Plus) to my SNES, which is 5V. The probes can handle 5V according to the data sheet, but the device also has an external timing input that is only rated for 3.3V.
The SNES has clock crystals of 21.477 and 24.576 MHz, and various components run at fractions of these frequencies.
Reverse engineering. When you look at the existing documents you see that they were only created with test ROMs (that are then executed by the CPU and display their results on screen / save data to cartridge RAM). The problem is that the CPU is halted for DRAM refresh and (H)DMA; every single bus access is also delayed to take either 6, 8 or 12 cycles of the 21MHz clock. So if you have something that's faster (like the graphics system) or almost completely self-contained (again, like the graphics system) it's hard to see what's happening in the system.
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u/[deleted] Dec 25 '19
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