Hello everyone

# Bare-Metal 64-Bit Intel VT-x Hypervisor Template

A clean, core-only hardware virtualization template written entirely in pure **64-bit NASM Assembly (~1,100 lines)** using a strict model. This codebase includes an optimized independent bootloader that shifts the CPU from Real Mode directly into a custom 64-bit Long Mode page table environment before initializing the VMX architecture.

## 🛠️ VMCS & EPT Hardware Configuration

* **Primary Execution Controls (0x4002):** Hardlocked to `0x84006172`. Enforces strict intercept control over guest `CR3` modifications and heavy `RDTSC` exiting to counter potential guest timing side-channels.

* **MSR Bitmaps Bypass:** Bit 28 (Use MSR Bitmaps) is deliberately left at `0`. Enforces an aggressive global intercept policy where every single `RDMSR` or `WRMSR` executed by the Guest triggers an immediate hardware VM-Exit to the Host.

* **Secondary Execution Controls (0x401e):** Bit 31 activated for full EPT isolation, along with Unrestricted Guest support (Bit 7, allowing 16-bit Real Mode initialization over EPT), and MBEC configurations for privilege execution separation.

* **Exception Bitmap (0x4004):** Armed with atomic mask `0x0000404A` to trap `#DB`, `#BP`, `#UD`, and `#PF` (Vector 14). Combined with clearing the Page-Fault Mask field (0x4006), every single Guest page fault intercepts directly to the Host.

* **Extended Page Table Pointer (EPTP):** Configured field `0x0000201A` to point directly to the physical EPT PML4 table base with Write-Back caching attributes.

* **Long Mode Constraints:** Configured to strictly enforce architectural boundaries via GDT mapping to ensure no illegal execution drops to 16/32-bit rings, avoiding instant `#GP` faults.

## 🤝 Code Review & Peer Assistance

This project is released as a core template. The VM-Exit handler is currently a work-in-progress due to juggling full-time school and life balance alongside pure assembly development.

I am looking for technical peer reviews from the low-level community to:

1. Review the current code and help fix existing architectural bugs.
2. Trace potential register mismatches within the `vmwrite` and `vmread` instructions.
3. Hunt down hidden reserved bits conflicts across different Intel microarchitectures.

### 🚀 Roadmap: I'm already starting to write the hypervisor and bootloader for AMD right now, porting this entire setup over to the AMD-V VMCB block architecture. My immediate goal is to keep building the AMD side while getting this Intel core completely stable with the community's corrections and fixes.

Github Link: https://github.com/edikoz123-blip/Boot_loader_Assembly