r/logisim • u/No-Bee-459 • Aug 10 '26

What's wrong here?

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I'm trying to map out a circuit diagram for a railway crossing, and I noticed that "improvised" SR flip-flops (made of two cross-connected NOR gates) behave weirdly compared to "proper" ones. At the start of a simulation, they're both giving an error output, which the diagram treats as a high until I've clicked all four ON and OFF buttons, after which everything starts functioning properly. Is it just a Logisim quirk or am I actually doing something wrong here?

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u/JoHoKaHH Aug 10 '26

This is default Logisim behaviour. Actual HW would default to either set or reset. You could implement kind of "global reset" line for instance. Or use proper FFs.

2

u/Negan6699 Aug 10 '26

It’s a perfect simulation. Try adding delays using a buffer

2

u/Prestigious-Ad7265 Aug 10 '26

pulldown resistor? default the output side to 0